1 // SPDX-License-Identifier: GPL-2.0
3  * StarFive JH7110 Image-Signal-Process Clock Driver
5  * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
9 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/starfive,jh7110-crg.h>
17 #include "clk-starfive-jh7110.h"
70 	top_rsts = devm_reset_control_array_get_shared(priv->dev);  in jh7110_isp_top_rst_init()
72 		return dev_err_probe(priv->dev, PTR_ERR(top_rsts),  in jh7110_isp_top_rst_init()
83 	clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);  in jh7110_ispcrg_suspend()
92 	return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks);  in jh7110_ispcrg_resume()
107 	priv = devm_kzalloc(&pdev->dev,  in jh7110_ispcrg_probe()
111 		return -ENOMEM;  in jh7110_ispcrg_probe()
113 	top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL);  in jh7110_ispcrg_probe()
115 		return -ENOMEM;  in jh7110_ispcrg_probe()
117 	spin_lock_init(&priv->rmw_lock);  in jh7110_ispcrg_probe()
118 	priv->num_reg = JH7110_ISPCLK_END;  in jh7110_ispcrg_probe()
119 	priv->dev = &pdev->dev;  in jh7110_ispcrg_probe()
120 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in jh7110_ispcrg_probe()
121 	if (IS_ERR(priv->base))  in jh7110_ispcrg_probe()
122 		return PTR_ERR(priv->base);  in jh7110_ispcrg_probe()
124 	top->top_clks = jh7110_isp_top_clks;  in jh7110_ispcrg_probe()
125 	top->top_clks_num = ARRAY_SIZE(jh7110_isp_top_clks);  in jh7110_ispcrg_probe()
126 	ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks);  in jh7110_ispcrg_probe()
128 		return dev_err_probe(priv->dev, ret, "failed to get main clocks\n");  in jh7110_ispcrg_probe()
129 	dev_set_drvdata(priv->dev, top);  in jh7110_ispcrg_probe()
132 	pm_runtime_enable(priv->dev);  in jh7110_ispcrg_probe()
133 	ret = pm_runtime_get_sync(priv->dev);  in jh7110_ispcrg_probe()
135 		return dev_err_probe(priv->dev, ret, "failed to turn on power\n");  in jh7110_ispcrg_probe()
152 		struct jh71x0_clk *clk = &priv->reg[idx];  in jh7110_ispcrg_probe()
154 		const char *fw_name[JH7110_ISPCLK_EXT_END - JH7110_ISPCLK_END] = {  in jh7110_ispcrg_probe()
165 				parents[i].hw = &priv->reg[pidx].hw;  in jh7110_ispcrg_probe()
167 				parents[i].fw_name = fw_name[pidx - JH7110_ISPCLK_END];  in jh7110_ispcrg_probe()
170 		clk->hw.init = &init;  in jh7110_ispcrg_probe()
171 		clk->idx = idx;  in jh7110_ispcrg_probe()
172 		clk->max_div = max & JH71X0_CLK_DIV_MASK;  in jh7110_ispcrg_probe()
174 		ret = devm_clk_hw_register(&pdev->dev, &clk->hw);  in jh7110_ispcrg_probe()
179 	ret = devm_of_clk_add_hw_provider(&pdev->dev, jh71x0_clk_get, priv);  in jh7110_ispcrg_probe()
183 	ret = jh7110_reset_controller_register(priv, "rst-isp", 3);  in jh7110_ispcrg_probe()
190 	pm_runtime_put_sync(priv->dev);  in jh7110_ispcrg_probe()
191 	pm_runtime_disable(priv->dev);  in jh7110_ispcrg_probe()
197 	pm_runtime_put_sync(&pdev->dev);  in jh7110_ispcrg_remove()
198 	pm_runtime_disable(&pdev->dev);  in jh7110_ispcrg_remove()
202 	{ .compatible = "starfive,jh7110-ispcrg" },
211 		.name = "clk-starfive-jh7110-isp",
219 MODULE_DESCRIPTION("StarFive JH7110 Image-Signal-Process clock driver");