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Searched +full:gamma +full:- +full:lut (Results 1 – 25 of 60) sorted by relevance

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/linux-6.14.4/drivers/gpu/drm/mediatek/
Dmtk_disp_gamma.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/soc/mediatek/mtk-cmdq.h>
35 /* For 10 bit LUT layout, R/G/B are in the same register */
40 /* For 12 bit LUT layout, R/G are in LUT, B is in LUT1 */
54 * struct mtk_disp_gamma - Display Gamma driver structure
69 struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); in mtk_gamma_clk_enable() local
71 return clk_prepare_enable(gamma->clk); in mtk_gamma_clk_enable()
76 struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); in mtk_gamma_clk_disable() local
78 clk_disable_unprepare(gamma->clk); in mtk_gamma_clk_disable()
83 struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); in mtk_gamma_get_lut_size() local
[all …]
Dmtk_disp_aal.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/soc/mediatek/mtk-cmdq.h>
40 * struct mtk_disp_aal - Display Adaptive Ambient Light driver structure
57 return clk_prepare_enable(aal->clk); in mtk_aal_clk_enable()
64 clk_disable_unprepare(aal->clk); in mtk_aal_clk_disable()
77 mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); in mtk_aal_config()
78 mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); in mtk_aal_config()
82 * mtk_aal_gamma_get_lut_size() - Get gamma LUT size for AAL
85 * Return: 0 if gamma control not supported in AAL or gamma LUT size
91 if (aal->data && aal->data->has_gamma) in mtk_aal_gamma_get_lut_size()
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_color.c38 * - Input gamma LUT (de-normalized)
39 * - Input CSC (normalized)
40 * - Surface degamma LUT (normalized)
41 * - Surface CSC (normalized)
42 * - Surface regamma LUT (normalized)
43 * - Output CSC (normalized)
49 * Plane CTM -> Plane degamma -> Plane CTM -> Plane regamma -> Plane CTM
51 * The input gamma LUT block isn't really applicable here since it operates
59 * support any CRTC props with correct blending with multiple planes - but we
64 * respective property is set to NULL. A linear DGM/RGM LUT should also
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/linux-6.14.4/drivers/gpu/drm/
Ddrm_color_mgmt.c42 * Blob property to set the degamma lookup table (LUT) mapping pixel data
45 * Hardware might choose not to use the full precision of the LUT elements
46 * nor use all the elements of the LUT (for example the hardware might
47 * choose to interpolate between LUT[0] and LUT[4]).
50 * linear/pass-thru gamma table should be used. This is generally the
51 * driver boot-up state too. Drivers can access this blob through
57 * hardware). If drivers support multiple LUT sizes then they should
58 * publish the largest size, and sub-sample smaller sized LUTs (e.g. for
59 * split-gamma modes) appropriately.
63 * pixel data after the lookup through the degamma LUT and before the
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/core/
Ddc_surface.c42 plane_state->ctx = ctx; in dc_plane_construct()
44 plane_state->gamma_correction.is_identity = true; in dc_plane_construct()
46 plane_state->in_transfer_func.type = TF_TYPE_BYPASS; in dc_plane_construct()
48 plane_state->in_shaper_func.type = TF_TYPE_BYPASS; in dc_plane_construct()
50 plane_state->lut3d_func.state.raw = 0; in dc_plane_construct()
52 plane_state->blend_tf.type = TF_TYPE_BYPASS; in dc_plane_construct()
54 plane_state->pre_multiplied_alpha = true; in dc_plane_construct()
73 for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) { in dc_plane_get_pipe_mask()
74 struct pipe_ctx *pipe_ctx = &dc_state->res_ctx.pipe_ctx[i]; in dc_plane_get_pipe_mask()
76 if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp) in dc_plane_get_pipe_mask()
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_ipp.c31 (ipp_dce->regs->reg)
35 ipp_dce->ipp_shift->field_name, ipp_dce->ipp_mask->field_name
38 ipp_dce->base.ctx
53 REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable); in dce_ipp_cursor_set_position()
56 CURSOR_X_POSITION, position->x, in dce_ipp_cursor_set_position()
57 CURSOR_Y_POSITION, position->y); in dce_ipp_cursor_set_position()
60 CURSOR_HOT_SPOT_X, position->x_hotspot, in dce_ipp_cursor_set_position()
61 CURSOR_HOT_SPOT_Y, position->y_hotspot); in dce_ipp_cursor_set_position()
78 switch (attributes->color_format) { in dce_ipp_cursor_set_attributes()
98 CURSOR_2X_MAGNIFY, attributes->attribute_flags.bits.ENABLE_MAGNIFICATION, in dce_ipp_cursor_set_attributes()
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
Ddcn10_dpp_cm.c43 dpp->tf_regs->reg
46 dpp->base.ctx
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
129 dpp->base.ctx, in program_gamut_remap()
139 dpp->base.ctx, in program_gamut_remap()
149 dpp->base.ctx, in program_gamut_remap()
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/linux-6.14.4/Documentation/devicetree/bindings/display/rockchip/
Drockchip-vop2.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <[email protected]>
21 - rockchip,rk3566-vop
22 - rockchip,rk3568-vop
23 - rockchip,rk3588-vop
27 - description:
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/linux-6.14.4/drivers/gpu/drm/i915/display/
Dintel_color.c37 * Program non-arming double buffered color management registers
99 #define CTM_COEFF_LIMITED_RANGE ((235ULL - 16ULL) * CTM_COEFF_1_0 / 255)
102 #define CTM_COEFF_ABS(coeff) ((coeff) & (CTM_COEFF_SIGN - 1))
115 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=0 -> 1/2, 0, 1/2
116 * CSC_MODE_YUV_TO_RGB=0 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/2, 1/16, 1/2
117 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=0 -> 0, 0, 0
118 * CSC_MODE_YUV_TO_RGB=1 + CSC_BLACK_SCREEN_OFFSET=1 -> 1/16, 1/16, 1/16
131 (clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
134 #define ILK_CSC_COEFF_LIMITED_RANGE ((235 - 16) << (12 - 8)) /* exponent 0 */
135 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 << (12 - 8))
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Dhsw_ips.c1 // SPDX-License-Identifier: MIT
19 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_ips_enable()
20 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in hsw_ips_enable()
23 if (!crtc_state->ips_enabled) in hsw_ips_enable()
31 drm_WARN_ON(display->drm, in hsw_ips_enable()
32 !(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); in hsw_ips_enable()
36 if (display->ips.false_color) in hsw_ips_enable()
40 drm_WARN_ON(display->drm, in hsw_ips_enable()
41 snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, in hsw_ips_enable()
59 drm_err(display->drm, in hsw_ips_enable()
[all …]
/linux-6.14.4/include/drm/
Ddrm_color_mgmt.h34 * drm_color_lut_extract - clamp and round LUT entries
36 * @bit_precision: number of bits the hw LUT supports
38 * Extract a degamma/gamma LUT value provided by user (in the form of
40 * hardware, following OpenGL int<->float conversion rules
41 * (see eg. OpenGL 4.6 specification - 2.3.5 Fixed-Point Data Conversions).
46 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(user_input, (1 << bit_precision) - 1), in drm_color_lut_extract()
47 (1 << 16) - 1); in drm_color_lut_extract()
49 return DIV_ROUND_CLOSEST(user_input * ((1 << bit_precision) - 1), in drm_color_lut_extract()
50 (1 << 16) - 1); in drm_color_lut_extract()
64 * drm_color_lut_size - calculate the number of entries in the LUT
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/linux-6.14.4/drivers/gpu/drm/renesas/rcar-du/
Drcar_cmm.c1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Display Unit Color Management Module
27 * @lut: 1D-LUT state
28 * @lut.enabled: 1D-LUT enabled flag
32 } lut; member
37 return ioread32(rcmm->base + reg); in rcar_cmm_read()
42 iowrite32(data, rcmm->base + reg); in rcar_cmm_write()
46 * rcar_cmm_lut_write() - Scale the DRM LUT table entries to hardware precision
49 * @drm_lut: Pointer to the DRM LUT table
66 * rcar_cmm_setup() - Configure the CMM unit
[all …]
/linux-6.14.4/drivers/gpu/drm/arm/
Dmalidp_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
29 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_mode_valid()
35 long rate, req_rate = mode->crtc_clock * 1000; in malidp_crtc_mode_valid()
38 rate = clk_round_rate(hwdev->pxlclk, req_rate); in malidp_crtc_mode_valid()
53 struct malidp_hw_device *hwdev = malidp->dev; in malidp_crtc_atomic_enable()
55 int err = pm_runtime_get_sync(crtc->dev->dev); in malidp_crtc_atomic_enable()
62 drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm); in malidp_crtc_atomic_enable()
63 clk_prepare_enable(hwdev->pxlclk); in malidp_crtc_atomic_enable()
66 clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000); in malidp_crtc_atomic_enable()
68 hwdev->hw->modeset(hwdev, &vm); in malidp_crtc_atomic_enable()
[all …]
/linux-6.14.4/drivers/staging/media/ipu3/include/uapi/
Dintel-ipu3.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* Copyright (C) 2017 - 2018 Intel Corporation */
11 /* Vendor specific - used for IPU3 camera sub-system */
17 /* from include/uapi/linux/v4l2-controls.h */
26 #define IPU3_UAPI_GRID_START_MASK ((1 << 12) - 1)
34 * struct ipu3_uapi_grid_config - Grid plane config
56 * create a grid-based output, and the data is then divided into "slices".
71 * struct ipu3_uapi_awb_set_item - Memory layout for each cell in AWB
108 * struct ipu3_uapi_awb_raw_buffer - AWB raw buffer
119 * struct ipu3_uapi_awb_config_s - AWB config
[all …]
/linux-6.14.4/drivers/gpu/drm/ci/xfails/
Dmediatek-mt8183-fails.txt1 core_setmaster@master-drop-set-shared-fd,Fail
2 dumb_buffer@create-clear,Crash
6 fbdev@unaligned-read,Fail
7 kms_bw@connected-linear-tiling-1-displays-1920x1080p,Fail
8 kms_bw@connected-linear-tiling-1-displays-2160x1440p,Fail
9 kms_bw@connected-linear-tiling-1-displays-2560x1440p,Fail
10 kms_bw@linear-tiling-1-displays-1920x1080p,Fail
11 kms_bw@linear-tiling-1-displays-3840x2160p,Fail
12 kms_color@invalid-gamma-lut-sizes,Fail
13 kms_flip@flip-vs-panning-vs-hang,Fail
[all …]
Dmediatek-mt8173-fails.txt4 kms_bw@connected-linear-tiling-1-displays-1920x1080p,Fail
5 kms_bw@connected-linear-tiling-1-displays-2160x1440p,Fail
6 kms_bw@connected-linear-tiling-1-displays-2560x1440p,Fail
7 kms_bw@connected-linear-tiling-1-displays-3840x2160p,Fail
8 kms_bw@connected-linear-tiling-2-displays-1920x1080p,Fail
9 kms_bw@connected-linear-tiling-2-displays-2160x1440p,Fail
10 kms_bw@connected-linear-tiling-2-displays-2560x1440p,Fail
11 kms_bw@connected-linear-tiling-2-displays-3840x2160p,Fail
12 kms_bw@linear-tiling-1-displays-1920x1080p,Fail
13 kms_bw@linear-tiling-1-displays-2160x1440p,Fail
[all …]
/linux-6.14.4/include/uapi/linux/media/raspberrypi/
Dpisp_be_config.h1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
5 * Copyright (C) 2021 - Raspberry Pi Ltd
97 * struct pisp_be_global_config - PiSP global enable bitmaps
111 * struct pisp_be_input_buffer_config - PiSP Back End input buffer
120 * struct pisp_be_dpc_config - PiSP Back End DPC config
138 * struct pisp_be_geq_config - PiSP Back End GEQ config
150 #define PISP_BE_GEQ_SLOPE ((1 << 10) - 1)
158 * struct pisp_be_tdn_input_buffer_config - PiSP Back End TDN input buffer
167 * struct pisp_be_tdn_config - PiSP Back End TDN config
190 * struct pisp_be_tdn_output_buffer_config - PiSP Back End TDN output buffer
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/inc/hw/
Dmpc.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
30 * that performs blending of multiple planes, using global and per-pixel alpha.
31 * It also performs post-blending color correction operations according to the
32 * hardware capabilities, such as color transformation matrix and gamma 1D and
33 * 3D LUT.
36 * supporting "M MPC inputs -> N MPC outputs" flexible composition
39 * - Programmable blending structure to allow software controlled blending and
41 * - Programmable window location of each DPP in active region of display;
42 * - Combining multiple DPP pipes in one active region when a single DPP pipe
44 * - Combining multiple DPP from different SLS with blending;
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/
Ddc.h2 * Copyright 2012-2023 Advanced Micro Devices, Inc.
108 // for example, 1080p -> 8K is 4.0, or 4000 raw value
116 // for example, 8K -> 1080p is 0.25, or 250 raw value
128 * DOC: color-management-caps
133 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
140 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
143 * @gamma2_2: standard gamma
145 * @hlg: hybrid log–gamma transfer function
156 * struct dpp_color_caps - color pipeline capabilities for display pipe and
160 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs,
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
Ddcn20_dpp.c42 dpp->tf_regs->reg
45 dpp->base.ctx
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
57 DPP_CLOCK_ENABLE, &s->is_enabled); in dpp20_read_state()
59 // Degamma LUT (RAM) in dpp20_read_state()
61 CM_DGAM_LUT_MODE, &s->dgam_lut_mode); in dpp20_read_state()
63 // Shaper LUT (RAM), 3D LUT (mode, bit-depth, size) in dpp20_read_state()
65 CM_SHAPER_LUT_MODE, &s->shaper_lut_mode); in dpp20_read_state()
67 CM_3DLUT_CONFIG_STATUS, &s->lut3d_mode, in dpp20_read_state()
68 CM_3DLUT_30BIT_EN, &s->lut3d_bit_depth); in dpp20_read_state()
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/modules/color/
Dcolor_gamma.c30 /* When calculating LUT values the first region and at least one subsequent
43 // The last point is above PQ formula range (0-125 in normalized FP16)
46 // first couple points are 0 - HW LUT is mirrored around zero, so making first
48 // min nonzero value below (216825) is a little under 12-bit PQ code 1.
141 /* Helper to optimize gamma calculation, only use in translate_from_linear, in
146 * X[i] = 2 * X[i-NUM_PTS_IN_REGION] for i>=16
147 * The other fact is that (2x)^gamma = 2^gamma * x^gamma
148 * So we compute and save x^gamma for the first 16 regions, and for every next region
149 * just multiply with 2^gamma which can be computed once, and save the result so we
164 /* one-time setup of X points */
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_mode.h40 #include <linux/i2c-algo-bit.h>
128 /* amdgpu gpio-based i2c
150 /* uses multi-media i2c engine */
317 /* DVI-I properties */
346 /* Driver-private color mgmt props */
348 /* @plane_degamma_lut_property: Plane property to set a degamma LUT to
354 * size of degamma LUT as supported by the driver (read-only).
358 * @plane_degamma_tf_property: Plane pre-defined transfer function to
369 * @shaper_lut_property: Plane property to set pre-blending shaper LUT
370 * that converts color content before 3D LUT. If
[all …]
/linux-6.14.4/drivers/gpu/drm/omapdrm/
Domap_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
51 /* -----------------------------------------------------------------------------
58 return &omap_crtc->vm; in omap_crtc_timings()
64 return omap_crtc->channel; in omap_crtc_channel()
73 spin_lock_irqsave(&crtc->dev->event_lock, flags); in omap_crtc_is_pending()
74 pending = omap_crtc->pending; in omap_crtc_is_pending()
75 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in omap_crtc_is_pending()
88 return wait_event_timeout(omap_crtc->pending_wait, in omap_crtc_wait_pending()
93 /* -----------------------------------------------------------------------------
[all …]
/linux-6.14.4/drivers/gpu/drm/mgag200/
Dmgag200_mode.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/iosys-map.h>
40 switch (format->format) { in mgag200_crtc_set_gamma_linear()
64 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n", in mgag200_crtc_set_gamma_linear()
65 &format->format); in mgag200_crtc_set_gamma_linear()
72 struct drm_color_lut *lut) in mgag200_crtc_set_gamma() argument
78 switch (format->format) { in mgag200_crtc_set_gamma()
80 /* Use better interpolation, to take 32 values from lut[0] to lut[255] */ in mgag200_crtc_set_gamma()
82 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 8 + i / 4].red >> 8); in mgag200_crtc_set_gamma()
83 WREG8(DAC_INDEX + MGA1064_COL_PAL, lut[i * 4 + i / 16].green >> 8); in mgag200_crtc_set_gamma()
[all …]
/linux-6.14.4/Documentation/gpu/amdgpu/display/
Ddisplay-manager.rst8 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
17 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
20 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
26 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
29 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
32 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
38 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
41 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
47 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
[all …]

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