1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
51 /* -----------------------------------------------------------------------------
58 	return &omap_crtc->vm;  in omap_crtc_timings()
64 	return omap_crtc->channel;  in omap_crtc_channel()
73 	spin_lock_irqsave(&crtc->dev->event_lock, flags);  in omap_crtc_is_pending()
74 	pending = omap_crtc->pending;  in omap_crtc_is_pending()
75 	spin_unlock_irqrestore(&crtc->dev->event_lock, flags);  in omap_crtc_is_pending()
88 	return wait_event_timeout(omap_crtc->pending_wait,  in omap_crtc_wait_pending()
93 /* -----------------------------------------------------------------------------
98  * Manager-ops, callbacks from output when they need to configure
105 	dispc_mgr_enable(priv->dispc, channel, true);  in omap_crtc_dss_start_update()
111 	struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);  in omap_crtc_set_enabled()
112 	struct drm_device *dev = crtc->dev;  in omap_crtc_set_enabled()
113 	struct omap_drm_private *priv = dev->dev_private;  in omap_crtc_set_enabled()
115 	enum omap_channel channel = omap_crtc->channel;  in omap_crtc_set_enabled()
120 	if (WARN_ON(omap_crtc->enabled == enable))  in omap_crtc_set_enabled()
123 	if (omap_state->manually_updated) {  in omap_crtc_set_enabled()
125 		omap_crtc->enabled = enable;  in omap_crtc_set_enabled()
129 	if (omap_crtc->pipe->output->type == OMAP_DISPLAY_TYPE_HDMI) {  in omap_crtc_set_enabled()
130 		dispc_mgr_enable(priv->dispc, channel, enable);  in omap_crtc_set_enabled()
131 		omap_crtc->enabled = enable;  in omap_crtc_set_enabled()
135 	if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {  in omap_crtc_set_enabled()
140 		omap_crtc->ignore_digit_sync_lost = true;  in omap_crtc_set_enabled()
143 	framedone_irq = dispc_mgr_get_framedone_irq(priv->dispc,  in omap_crtc_set_enabled()
145 	vsync_irq = dispc_mgr_get_vsync_irq(priv->dispc, channel);  in omap_crtc_set_enabled()
165 	dispc_mgr_enable(priv->dispc, channel, enable);  in omap_crtc_set_enabled()
166 	omap_crtc->enabled = enable;  in omap_crtc_set_enabled()
170 		dev_err(dev->dev, "%s: timeout waiting for %s\n",  in omap_crtc_set_enabled()
171 				omap_crtc->name, enable ? "enable" : "disable");  in omap_crtc_set_enabled()
174 	if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {  in omap_crtc_set_enabled()
175 		omap_crtc->ignore_digit_sync_lost = false;  in omap_crtc_set_enabled()
184 	struct drm_crtc *crtc = priv->channels[channel]->crtc;  in omap_crtc_dss_enable()
187 	dispc_mgr_set_timings(priv->dispc, omap_crtc->channel,  in omap_crtc_dss_enable()
188 					 &omap_crtc->vm);  in omap_crtc_dss_enable()
189 	omap_crtc_set_enabled(&omap_crtc->base, true);  in omap_crtc_dss_enable()
196 	struct drm_crtc *crtc = priv->channels[channel]->crtc;  in omap_crtc_dss_disable()
199 	omap_crtc_set_enabled(&omap_crtc->base, false);  in omap_crtc_dss_disable()
206 	struct drm_crtc *crtc = priv->channels[channel]->crtc;  in omap_crtc_dss_set_timings()
209 	DBG("%s", omap_crtc->name);  in omap_crtc_dss_set_timings()
210 	omap_crtc->vm = *vm;  in omap_crtc_dss_set_timings()
217 	struct drm_crtc *crtc = priv->channels[channel]->crtc;  in omap_crtc_dss_set_lcd_config()
220 	DBG("%s", omap_crtc->name);  in omap_crtc_dss_set_lcd_config()
221 	dispc_mgr_set_lcd_config(priv->dispc, omap_crtc->channel,  in omap_crtc_dss_set_lcd_config()
229 	struct drm_crtc *crtc = priv->channels[channel]->crtc;  in omap_crtc_dss_register_framedone()
231 	struct drm_device *dev = omap_crtc->base.dev;  in omap_crtc_dss_register_framedone()
233 	if (omap_crtc->framedone_handler)  in omap_crtc_dss_register_framedone()
234 		return -EBUSY;  in omap_crtc_dss_register_framedone()
236 	dev_dbg(dev->dev, "register framedone %s", omap_crtc->name);  in omap_crtc_dss_register_framedone()
238 	omap_crtc->framedone_handler = handler;  in omap_crtc_dss_register_framedone()
239 	omap_crtc->framedone_handler_data = data;  in omap_crtc_dss_register_framedone()
248 	struct drm_crtc *crtc = priv->channels[channel]->crtc;  in omap_crtc_dss_unregister_framedone()
250 	struct drm_device *dev = omap_crtc->base.dev;  in omap_crtc_dss_unregister_framedone()
252 	dev_dbg(dev->dev, "unregister framedone %s", omap_crtc->name);  in omap_crtc_dss_unregister_framedone()
254 	WARN_ON(omap_crtc->framedone_handler != handler);  in omap_crtc_dss_unregister_framedone()
255 	WARN_ON(omap_crtc->framedone_handler_data != data);  in omap_crtc_dss_unregister_framedone()
257 	omap_crtc->framedone_handler = NULL;  in omap_crtc_dss_unregister_framedone()
258 	omap_crtc->framedone_handler_data = NULL;  in omap_crtc_dss_unregister_framedone()
261 /* -----------------------------------------------------------------------------
269 	if (omap_crtc->ignore_digit_sync_lost) {  in omap_crtc_error_irq()
275 	DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);  in omap_crtc_error_irq()
281 	struct drm_device *dev = omap_crtc->base.dev;  in omap_crtc_vblank_irq()
282 	struct omap_drm_private *priv = dev->dev_private;  in omap_crtc_vblank_irq()
285 	spin_lock(&crtc->dev->event_lock);  in omap_crtc_vblank_irq()
290 	if (dispc_mgr_go_busy(priv->dispc, omap_crtc->channel)) {  in omap_crtc_vblank_irq()
291 		spin_unlock(&crtc->dev->event_lock);  in omap_crtc_vblank_irq()
296 	if (omap_crtc->event) {  in omap_crtc_vblank_irq()
297 		drm_crtc_send_vblank_event(crtc, omap_crtc->event);  in omap_crtc_vblank_irq()
298 		omap_crtc->event = NULL;  in omap_crtc_vblank_irq()
301 	pending = omap_crtc->pending;  in omap_crtc_vblank_irq()
302 	omap_crtc->pending = false;  in omap_crtc_vblank_irq()
303 	spin_unlock(&crtc->dev->event_lock);  in omap_crtc_vblank_irq()
309 	wake_up(&omap_crtc->pending_wait);  in omap_crtc_vblank_irq()
311 	DBG("%s: apply done", omap_crtc->name);  in omap_crtc_vblank_irq()
318 	if (!omap_crtc->framedone_handler)  in omap_crtc_framedone_irq()
321 	omap_crtc->framedone_handler(omap_crtc->framedone_handler_data);  in omap_crtc_framedone_irq()
323 	spin_lock(&crtc->dev->event_lock);  in omap_crtc_framedone_irq()
325 	if (omap_crtc->event) {  in omap_crtc_framedone_irq()
326 		drm_crtc_send_vblank_event(crtc, omap_crtc->event);  in omap_crtc_framedone_irq()
327 		omap_crtc->event = NULL;  in omap_crtc_framedone_irq()
329 	omap_crtc->pending = false;  in omap_crtc_framedone_irq()
330 	spin_unlock(&crtc->dev->event_lock);  in omap_crtc_framedone_irq()
333 	wake_up(&omap_crtc->pending_wait);  in omap_crtc_framedone_irq()
339 	struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);  in omap_crtc_flush()
341 	if (!omap_state->manually_updated)  in omap_crtc_flush()
344 	if (!delayed_work_pending(&omap_crtc->update_work))  in omap_crtc_flush()
345 		schedule_delayed_work(&omap_crtc->update_work, 0);  in omap_crtc_flush()
352 	struct omap_dss_device *dssdev = omap_crtc->pipe->output;  in omap_crtc_manual_display_update()
353 	struct drm_device *dev = omap_crtc->base.dev;  in omap_crtc_manual_display_update()
356 	if (!dssdev || !dssdev->dsi_ops || !dssdev->dsi_ops->update)  in omap_crtc_manual_display_update()
359 	ret = dssdev->dsi_ops->update(dssdev);  in omap_crtc_manual_display_update()
361 		spin_lock_irq(&dev->event_lock);  in omap_crtc_manual_display_update()
362 		omap_crtc->pending = false;  in omap_crtc_manual_display_update()
363 		spin_unlock_irq(&dev->event_lock);  in omap_crtc_manual_display_update()
364 		wake_up(&omap_crtc->pending_wait);  in omap_crtc_manual_display_update()
376 		ret = -ret;  in omap_crtc_s31_32_to_s2_8()
384 	cpr->rr = omap_crtc_s31_32_to_s2_8(ctm->matrix[0]);  in omap_crtc_cpr_coefs_from_ctm()
385 	cpr->rg = omap_crtc_s31_32_to_s2_8(ctm->matrix[1]);  in omap_crtc_cpr_coefs_from_ctm()
386 	cpr->rb = omap_crtc_s31_32_to_s2_8(ctm->matrix[2]);  in omap_crtc_cpr_coefs_from_ctm()
387 	cpr->gr = omap_crtc_s31_32_to_s2_8(ctm->matrix[3]);  in omap_crtc_cpr_coefs_from_ctm()
388 	cpr->gg = omap_crtc_s31_32_to_s2_8(ctm->matrix[4]);  in omap_crtc_cpr_coefs_from_ctm()
389 	cpr->gb = omap_crtc_s31_32_to_s2_8(ctm->matrix[5]);  in omap_crtc_cpr_coefs_from_ctm()
390 	cpr->br = omap_crtc_s31_32_to_s2_8(ctm->matrix[6]);  in omap_crtc_cpr_coefs_from_ctm()
391 	cpr->bg = omap_crtc_s31_32_to_s2_8(ctm->matrix[7]);  in omap_crtc_cpr_coefs_from_ctm()
392 	cpr->bb = omap_crtc_s31_32_to_s2_8(ctm->matrix[8]);  in omap_crtc_cpr_coefs_from_ctm()
397 	struct omap_drm_private *priv = crtc->dev->dev_private;  in omap_crtc_write_crtc_properties()
407 	if (crtc->state->ctm) {  in omap_crtc_write_crtc_properties()
408 		struct drm_color_ctm *ctm = crtc->state->ctm->data;  in omap_crtc_write_crtc_properties()
416 	dispc_mgr_setup(priv->dispc, omap_crtc->channel, &info);  in omap_crtc_write_crtc_properties()
419 /* -----------------------------------------------------------------------------
427 	DBG("%s", omap_crtc->name);  in omap_crtc_destroy()
438 	WARN_ON(omap_crtc->pending);  in omap_crtc_arm_event()
439 	omap_crtc->pending = true;  in omap_crtc_arm_event()
441 	if (crtc->state->event) {  in omap_crtc_arm_event()
442 		omap_crtc->event = crtc->state->event;  in omap_crtc_arm_event()
443 		crtc->state->event = NULL;  in omap_crtc_arm_event()
450 	struct omap_drm_private *priv = crtc->dev->dev_private;  in omap_crtc_atomic_enable()
452 	struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);  in omap_crtc_atomic_enable()
455 	DBG("%s", omap_crtc->name);  in omap_crtc_atomic_enable()
457 	dispc_runtime_get(priv->dispc);  in omap_crtc_atomic_enable()
460 	if (omap_state->manually_updated)  in omap_crtc_atomic_enable()
468 	spin_lock_irq(&crtc->dev->event_lock);  in omap_crtc_atomic_enable()
470 	spin_unlock_irq(&crtc->dev->event_lock);  in omap_crtc_atomic_enable()
476 	struct omap_drm_private *priv = crtc->dev->dev_private;  in omap_crtc_atomic_disable()
478 	struct drm_device *dev = crtc->dev;  in omap_crtc_atomic_disable()
480 	DBG("%s", omap_crtc->name);  in omap_crtc_atomic_disable()
482 	spin_lock_irq(&crtc->dev->event_lock);  in omap_crtc_atomic_disable()
483 	if (crtc->state->event) {  in omap_crtc_atomic_disable()
484 		drm_crtc_send_vblank_event(crtc, crtc->state->event);  in omap_crtc_atomic_disable()
485 		crtc->state->event = NULL;  in omap_crtc_atomic_disable()
487 	spin_unlock_irq(&crtc->dev->event_lock);  in omap_crtc_atomic_disable()
489 	cancel_delayed_work(&omap_crtc->update_work);  in omap_crtc_atomic_disable()
492 		dev_warn(dev->dev, "manual display update did not finish!");  in omap_crtc_atomic_disable()
496 	dispc_runtime_put(priv->dispc);  in omap_crtc_atomic_disable()
502 	struct omap_drm_private *priv = crtc->dev->dev_private;  in omap_crtc_mode_valid()
514 	if (omap_crtc->pipe->output->type != OMAP_DISPLAY_TYPE_DSI) {  in omap_crtc_mode_valid()
515 		r = dispc_mgr_check_timings(priv->dispc,  in omap_crtc_mode_valid()
516 						       omap_crtc->channel,  in omap_crtc_mode_valid()
523 	if (priv->max_bandwidth) {  in omap_crtc_mode_valid()
535 		uint64_t bandwidth = mode->clock * 1000;  in omap_crtc_mode_valid()
538 		bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp;  in omap_crtc_mode_valid()
539 		bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal);  in omap_crtc_mode_valid()
545 		if (priv->max_bandwidth < bandwidth)  in omap_crtc_mode_valid()
555 	struct drm_display_mode *mode = &crtc->state->adjusted_mode;  in omap_crtc_mode_set_nofb()
558 	    omap_crtc->name, DRM_MODE_ARG(mode));  in omap_crtc_mode_set_nofb()
560 	drm_display_mode_to_videomode(mode, &omap_crtc->vm);  in omap_crtc_mode_set_nofb()
566 	struct omap_dss_device *dssdev = omap_crtc->pipe->output;  in omap_crtc_is_manually_updated()
568 	if (!dssdev || !dssdev->dsi_ops || !dssdev->dsi_ops->is_video_mode)  in omap_crtc_is_manually_updated()
571 	if (dssdev->dsi_ops->is_video_mode(dssdev))  in omap_crtc_is_manually_updated()
585 	if (crtc_state->color_mgmt_changed && crtc_state->degamma_lut) {  in omap_crtc_atomic_check()
586 		unsigned int length = crtc_state->degamma_lut->length /  in omap_crtc_atomic_check()
590 			return -EINVAL;  in omap_crtc_atomic_check()
594 						   crtc->primary);  in omap_crtc_atomic_check()
600 		omap_crtc_state->zpos = pri_state->zpos;  in omap_crtc_atomic_check()
601 		omap_crtc_state->rotation = pri_state->rotation;  in omap_crtc_atomic_check()
604 		omap_crtc_state->manually_updated = omap_crtc_is_manually_updated(crtc);  in omap_crtc_atomic_check()
618 	struct omap_drm_private *priv = crtc->dev->dev_private;  in omap_crtc_atomic_flush()
620 	struct omap_crtc_state *omap_crtc_state = to_omap_crtc_state(crtc->state);  in omap_crtc_atomic_flush()
623 	if (crtc->state->color_mgmt_changed) {  in omap_crtc_atomic_flush()
624 		struct drm_color_lut *lut = NULL;  in omap_crtc_atomic_flush()  local
627 		if (crtc->state->degamma_lut) {  in omap_crtc_atomic_flush()
628 			lut = (struct drm_color_lut *)  in omap_crtc_atomic_flush()
629 				crtc->state->degamma_lut->data;  in omap_crtc_atomic_flush()
630 			length = crtc->state->degamma_lut->length /  in omap_crtc_atomic_flush()
631 				sizeof(*lut);  in omap_crtc_atomic_flush()
633 		dispc_mgr_set_gamma(priv->dispc, omap_crtc->channel,  in omap_crtc_atomic_flush()
634 					       lut, length);  in omap_crtc_atomic_flush()
640 	if (!omap_crtc->enabled)  in omap_crtc_atomic_flush()
643 	DBG("%s: GO", omap_crtc->name);  in omap_crtc_atomic_flush()
645 	if (omap_crtc_state->manually_updated) {  in omap_crtc_atomic_flush()
647 		spin_lock_irq(&crtc->dev->event_lock);  in omap_crtc_atomic_flush()
650 		spin_unlock_irq(&crtc->dev->event_lock);  in omap_crtc_atomic_flush()
657 	spin_lock_irq(&crtc->dev->event_lock);  in omap_crtc_atomic_flush()
658 	dispc_mgr_go(priv->dispc, omap_crtc->channel);  in omap_crtc_atomic_flush()
660 	spin_unlock_irq(&crtc->dev->event_lock);  in omap_crtc_atomic_flush()
668 	struct omap_drm_private *priv = crtc->dev->dev_private;  in omap_crtc_atomic_set_property()
677 	plane_state = drm_atomic_get_plane_state(state->state, crtc->primary);  in omap_crtc_atomic_set_property()
681 	if (property == crtc->primary->rotation_property)  in omap_crtc_atomic_set_property()
682 		plane_state->rotation = val;  in omap_crtc_atomic_set_property()
683 	else if (property == priv->zorder_prop)  in omap_crtc_atomic_set_property()
684 		plane_state->zpos = val;  in omap_crtc_atomic_set_property()
686 		return -EINVAL;  in omap_crtc_atomic_set_property()
696 	struct omap_drm_private *priv = crtc->dev->dev_private;  in omap_crtc_atomic_get_property()
699 	if (property == crtc->primary->rotation_property)  in omap_crtc_atomic_get_property()
700 		*val = omap_state->rotation;  in omap_crtc_atomic_get_property()
701 	else if (property == priv->zorder_prop)  in omap_crtc_atomic_get_property()
702 		*val = omap_state->zpos;  in omap_crtc_atomic_get_property()
704 		return -EINVAL;  in omap_crtc_atomic_get_property()
713 	if (crtc->state)  in omap_crtc_reset()
714 		__drm_atomic_helper_crtc_destroy_state(crtc->state);  in omap_crtc_reset()
716 	kfree(crtc->state);  in omap_crtc_reset()
720 		__drm_atomic_helper_crtc_reset(crtc, &state->base);  in omap_crtc_reset()
728 	if (WARN_ON(!crtc->state))  in omap_crtc_duplicate_state()
731 	current_state = to_omap_crtc_state(crtc->state);  in omap_crtc_duplicate_state()
737 	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);  in omap_crtc_duplicate_state()
739 	state->zpos = current_state->zpos;  in omap_crtc_duplicate_state()
740 	state->rotation = current_state->rotation;  in omap_crtc_duplicate_state()
741 	state->manually_updated = current_state->manually_updated;  in omap_crtc_duplicate_state()
743 	return &state->base;  in omap_crtc_duplicate_state()
769 /* -----------------------------------------------------------------------------
785 	struct omap_drm_private *priv = dev->dev_private;  in omap_crtc_init()
791 	channel = pipe->output->dispc_channel;  in omap_crtc_init()
797 		return ERR_PTR(-ENOMEM);  in omap_crtc_init()
799 	crtc = &omap_crtc->base;  in omap_crtc_init()
801 	init_waitqueue_head(&omap_crtc->pending_wait);  in omap_crtc_init()
803 	omap_crtc->pipe = pipe;  in omap_crtc_init()
804 	omap_crtc->channel = channel;  in omap_crtc_init()
805 	omap_crtc->name = channel_names[channel];  in omap_crtc_init()
817 	INIT_DELAYED_WORK(&omap_crtc->update_work,  in omap_crtc_init()
823 		dev_err(dev->dev, "%s(): could not init crtc for: %s\n",  in omap_crtc_init()
824 			__func__, pipe->output->name);  in omap_crtc_init()
832 	 * 256 element gamma table for LCDs and 1024 element table for  in omap_crtc_init()
833 	 * OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma  in omap_crtc_init()
834 	 * tables so lets use that. Size of HW gamma table can be  in omap_crtc_init()
836 	 * gamma table is not supported.  in omap_crtc_init()
838 	if (dispc_mgr_gamma_size(priv->dispc, channel)) {  in omap_crtc_init()
845 	omap_plane_install_properties(crtc->primary, &crtc->base);  in omap_crtc_init()