1 // SPDX-License-Identifier: MIT
19 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_ips_enable()
20 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in hsw_ips_enable()
23 	if (!crtc_state->ips_enabled)  in hsw_ips_enable()
31 	drm_WARN_ON(display->drm,  in hsw_ips_enable()
32 		    !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));  in hsw_ips_enable()
36 	if (display->ips.false_color)  in hsw_ips_enable()
40 		drm_WARN_ON(display->drm,  in hsw_ips_enable()
41 			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,  in hsw_ips_enable()
59 			drm_err(display->drm,  in hsw_ips_enable()
67 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_ips_disable()
68 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in hsw_ips_disable()
71 	if (!crtc_state->ips_enabled)  in hsw_ips_disable()
75 		drm_WARN_ON(display->drm,  in hsw_ips_disable()
76 			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, 0));  in hsw_ips_disable()
83 			drm_err(display->drm,  in hsw_ips_disable()
99 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in hsw_ips_need_disable()
105 	if (!old_crtc_state->ips_enabled)  in hsw_ips_need_disable()
112 	 * Workaround : Do not read or write the pipe palette/gamma data while  in hsw_ips_need_disable()
113 	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.  in hsw_ips_need_disable()
115 	 * Disable IPS before we program the LUT.  in hsw_ips_need_disable()
119 	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)  in hsw_ips_need_disable()
122 	return !new_crtc_state->ips_enabled;  in hsw_ips_need_disable()
140 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in hsw_ips_need_enable()
146 	if (!new_crtc_state->ips_enabled)  in hsw_ips_need_enable()
153 	 * Workaround : Do not read or write the pipe palette/gamma data while  in hsw_ips_need_enable()
154 	 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.  in hsw_ips_need_enable()
156 	 * Re-enable IPS after the LUT has been programmed.  in hsw_ips_need_enable()
160 	    new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT)  in hsw_ips_need_enable()
167 	if (intel_crtc_needs_fastset(new_crtc_state) && old_crtc_state->inherited)  in hsw_ips_need_enable()
170 	return !old_crtc_state->ips_enabled;  in hsw_ips_need_enable()
190 	return HAS_IPS(display) && crtc->pipe == PIPE_A;  in hsw_crtc_supports_ips()
196 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_crtc_state_ips_capable()
197 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in hsw_crtc_state_ips_capable()
203 	if (!display->params.enable_ips)  in hsw_crtc_state_ips_capable()
206 	if (crtc_state->pipe_bpp > 24)  in hsw_crtc_state_ips_capable()
217 	    crtc_state->pixel_rate > display->cdclk.max_cdclk_freq * 95 / 100)  in hsw_crtc_state_ips_capable()
225 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);  in hsw_ips_min_cdclk()
234 	return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);  in hsw_ips_min_cdclk()
240 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in hsw_ips_compute_config()
244 	crtc_state->ips_enabled = false;  in hsw_ips_compute_config()
255 	if (crtc_state->crc_enabled)  in hsw_ips_compute_config()
259 	if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))  in hsw_ips_compute_config()
270 		if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)  in hsw_ips_compute_config()
274 	crtc_state->ips_enabled = true;  in hsw_ips_compute_config()
282 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_ips_get_config()
283 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in hsw_ips_get_config()
289 		crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE;  in hsw_ips_get_config()
296 		crtc_state->ips_enabled = true;  in hsw_ips_get_config()
305 	*val = display->ips.false_color;  in hsw_ips_debugfs_false_color_get()
317 	ret = drm_modeset_lock(&crtc->base.mutex, NULL);  in hsw_ips_debugfs_false_color_set()
321 	display->ips.false_color = val;  in hsw_ips_debugfs_false_color_set()
323 	crtc_state = to_intel_crtc_state(crtc->base.state);  in hsw_ips_debugfs_false_color_set()
325 	if (!crtc_state->hw.active)  in hsw_ips_debugfs_false_color_set()
328 	if (crtc_state->uapi.commit &&  in hsw_ips_debugfs_false_color_set()
329 	    !try_wait_for_completion(&crtc_state->uapi.commit->hw_done))  in hsw_ips_debugfs_false_color_set()
335 	drm_modeset_unlock(&crtc->base.mutex);  in hsw_ips_debugfs_false_color_set()
347 	struct intel_crtc *crtc = m->private;  in hsw_ips_debugfs_status_show()
349 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in hsw_ips_debugfs_status_show()
352 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);  in hsw_ips_debugfs_status_show()
355 		   str_yes_no(display->params.enable_ips));  in hsw_ips_debugfs_status_show()
366 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);  in hsw_ips_debugfs_status_show()
378 	debugfs_create_file("i915_ips_false_color", 0644, crtc->base.debugfs_entry,  in hsw_ips_crtc_debugfs_add()
381 	debugfs_create_file("i915_ips_status", 0444, crtc->base.debugfs_entry,  in hsw_ips_crtc_debugfs_add()