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/linux-6.14.4/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
[all …]
Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
[all …]
/linux-6.14.4/arch/riscv/boot/dts/microchip/
Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
[all …]
/linux-6.14.4/arch/riscv/boot/dts/starfive/
Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
[all …]
Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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/linux-6.14.4/arch/powerpc/boot/dts/
Dmicrowatt.dts1 /dts-v1/;
4 #size-cells = <0x02>;
5 #address-cells = <0x02>;
6 model-name = "microwatt";
7 compatible = "microwatt-soc";
13 reserved-memory {
14 #size-cells = <0x02>;
15 #address-cells = <0x02>;
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
[all …]
/linux-6.14.4/arch/arc/mm/
Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TLB Management (flush/create/diagnostics) for MMUv3 and MMUv4
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
22 unsigned int ver, pg_sz_k, s_pg_sz_m, pae, sets, ways; member
26 * Utility Routine to erase a J-TLB entry
63 /* Locate the TLB entry for this vaddr + ASID */ in tlb_entry_erase()
82 * This also sets up PD0 (vaddr, ASID..) for final commit in tlb_entry_insert()
89 * with existing location. This will cause Write CMD to over-write in tlb_entry_insert()
95 /* setup the other half of TLB entry (pfn, rwx..) */ in tlb_entry_insert()
101 * which doesn't flush uTLBs. I'd rather be safe than sorry. in tlb_entry_insert()
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/linux-6.14.4/Documentation/devicetree/bindings/riscv/
Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <[email protected]>
11 - Palmer Dabbelt <[email protected]>
12 - Conor Dooley <[email protected]>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/linux-6.14.4/arch/powerpc/kernel/
Dsetup_64.c1 // SPDX-License-Identifier: GPL-2.0-or-later
37 #include <asm/asm-prototypes.h>
63 #include <asm/text-patching.h>
68 #include <asm/feature-fixups.h>
101 * If we boot via kdump on a non-primary thread, in setup_tlb_core_data()
103 * set up this TLB. in setup_tlb_core_data()
108 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd; in setup_tlb_core_data()
112 * or e6500 tablewalk mode, or else TLB handlers in setup_tlb_core_data()
127 /* Look for ibm,smt-enabled OF option */
154 smt_option = of_get_property(dn, "ibm,smt-enabled", in check_smt_enabled()
[all …]
/linux-6.14.4/arch/parisc/include/asm/
Dropes.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <asm/parisc-device.h>
8 /* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
21 ** allocated and free'd/purged at a time might make this
33 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
34 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
38 unsigned long *res_hint; /* next avail IOVP - circular search */
85 unsigned int num_ioc; /* number of on-board IOC's */
98 static inline int IS_ASTRO(struct parisc_device *d) { in IS_ASTRO() argument
99 return d->id.hversion == ASTRO_RUNWAY_PORT; in IS_ASTRO()
[all …]
/linux-6.14.4/include/asm-generic/
Dtlb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
32 * Generic MMU-gather implementation.
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
49 * - tlb_gather_mmu() / tlb_gather_mmu_fullmm() / tlb_finish_mmu()
53 * Finish in particular will issue a (final) TLB invalidate and free
56 * - tlb_start_vma() / tlb_end_vma(); marks the start / end of a VMA
61 * - tlb_remove_table()
[all …]
/linux-6.14.4/arch/mips/mm/
Dc-octeon.c6 * Copyright (C) 2005-2007 Cavium Networks
20 #include <asm/cpu-features.h>
21 #include <asm/cpu-type.h>
33 * Octeon automatically flushes the dcache on tlb changes, so
49 * Flush local I-cache for the specified range.
58 * octeon_flush_icache_all_cores - Flush caches as necessary for all cores
82 mask = *mm_cpumask(vma->vm_mm); in octeon_flush_icache_all_cores()
109 * octeon_flush_cache_mm - flush all memory associated with a memory context.
133 * octeon_flush_cache_range - Flush a range out of a vma
142 if (vma->vm_flags & VM_EXEC) in octeon_flush_cache_range()
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/linux-6.14.4/Documentation/arch/x86/
Dpti.rst1 .. SPDX-License-Identifier: GPL-2.0
27 This approach helps to ensure that side-channel attacks leveraging
30 time. Once enabled at compile-time, it can be disabled at boot with
31 the 'nopti' or 'pti=' kernel parameters (see kernel-parameters.txt).
36 When PTI is enabled, the kernel manages two sets of page tables.
43 that any missed kernel->user CR3 switch will immediately crash
49 each CPU's copy of the area a compile-time-fixed virtual address.
65 Protection against side-channel attacks is important. But,
70 a. Each process now needs an order-1 PGD instead of order-0.
89 feature of the MMU allows different processes to share TLB
[all …]
Dsva.rst1 .. SPDX-License-Identifier: GPL-2.0
19 application page-faults. For more information please refer to the PCIe
25 mmu_notifier() support to keep the device TLB cache and the CPU cache in
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
55 ENQCMD works with non-posted semantics and carries a status back if the
67 A new thread-scoped MSR (IA32_PASID) provides the connection between
69 accesses an SVA-capable device, this MSR is initialized with a newly
70 allocated PASID. The driver for the device calls an IOMMU-specific API
[all …]
/linux-6.14.4/arch/openrisc/mm/
Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * OpenRISC tlb.c
11 * Copyright (C) 2010-2011 Julius Baxter <[email protected]>
12 * Copyright (C) 2010-2011 Jonas Bonn <[email protected]>
29 #define NO_CONTEXT -1
35 #define DTLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_DTLB_SETS-1))
36 #define ITLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_ITLB_SETS-1))
38 * Invalidate all TLB entries.
51 /* Determine number of sets for IMMU. */ in local_flush_tlb_all()
52 /* FIXME: Assumption is I & D nsets equal. */ in local_flush_tlb_all()
[all …]
/linux-6.14.4/arch/mips/kvm/
Dtlb.c6 * KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
7 * TLB handlers run from KSEG0
26 #include <asm/tlb.h>
42 struct mm_struct *gpa_mm = &vcpu->kvm->arch.gpa_mm; in kvm_mips_get_root_asid()
79 * clear_root_gid() - Set GuestCtl1.RID for normal root operation.
90 * set_root_gid_to_guest_gid() - Set GuestCtl1.RID to match GuestCtl1.ID.
92 * Sets the root GuestID to match the current guest GuestID, for TLB operation
93 * on the GPA->RPA mappings in the root TLB.
96 * possibly longer if TLB registers are modified.
121 /* Set root GuestID for root probe and write of guest TLB entry */ in kvm_vz_host_tlb_inv()
[all …]
/linux-6.14.4/drivers/parisc/
Dccio-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** ccio-dma.c:
4 ** DMA management routines for first generation cache-coherent machines.
9 ** (c) Copyright 2000 Hewlett-Packard Company
13 ** the I/O MMU - basically what x86 does.
16 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
17 ** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute.
19 ** o Doesn't work under PCX-U/U+ machines since they didn't follow
20 ** the coherency design originally worked out. Only PCX-W does.
34 #include <linux/dma-map-ops.h>
[all …]
/linux-6.14.4/arch/parisc/include/uapi/asm/
Dpdc.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 #define PDC_BAD_PROC -1 /* Called non-existent procedure*/
15 #define PDC_BAD_OPTION -2 /* Called with non-existent option */
16 #define PDC_ERROR -3 /* Call could not complete without an error */
17 #define PDC_NE_MOD -5 /* Module not found */
18 #define PDC_NE_CELL_MOD -7 /* Cell module not found */
19 #define PDC_NE_BOOTDEV -9 /* Cannot locate a console device or boot device */
20 #define PDC_INVALID_ARG -10 /* Called with an invalid argument */
21 #define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */
22 #define PDC_NOT_NARROW -17 /* Narrow mode not supported */
[all …]
/linux-6.14.4/drivers/misc/sgi-gru/
Dgrufault.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * FAULT HANDLER FOR GRU DETECTED TLB MISSES
7 * This file contains code that handles TLB misses within the GRU.
33 #define VTOP_INVALID -1
34 #define VTOP_RETRY -2
52 vma = vma_lookup(current->mm, vaddr); in gru_find_vma()
53 if (vma && vma->vm_ops == &gru_vm_ops) in gru_find_vma()
62 * - *gts with the mmap_lock locked for read and the GTS locked.
63 * - NULL if vaddr invalid OR is not a valid GSEG vaddr.
68 struct mm_struct *mm = current->mm; in gru_find_lock_gts()
[all …]
/linux-6.14.4/arch/parisc/mm/
Dfault.c39 * parisc_acctyp(unsigned int inst) --
40 * Given a PA-RISC memory access instruction, determine if the
81 * older PA-RISC platforms. The case where a block in parisc_acctyp()
89 * 01 Graphics flush write (IO space -> VM) in parisc_acctyp()
90 * 10 Graphics flush read (VM -> IO space) in parisc_acctyp()
91 * 11 Graphics flush read/write (VM <-> IO space) in parisc_acctyp()
106 * Data TLB miss fault/data page fault in parisc_acctyp()
127 * not, but I want it committed to CVS so I don't lose it :-)
130 if (tree->vm_start > addr) {
131 tree = tree->vm_avl_left;
[all …]
/linux-6.14.4/arch/microblaze/include/asm/
Dpgtable.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2008-2009 Michal Simek <[email protected]>
4 * Copyright (C) 2008-2009 PetaLogix
17 #include <asm-generic/pgtable-nopmd.h>
60 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash
64 * We use the hash table as an extended TLB, i.e. a cache of currently
65 * active mappings. We maintain a two-level page table tree, much
67 * management code. Low-level assembler code in hashtable.S
74 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The
75 * instruction and data sides share a unified, 64-entry, semi-associative
[all …]
/linux-6.14.4/Documentation/driver-api/media/drivers/
Dipu6.rst1 .. SPDX-License-Identifier: GPL-2.0
34 ------------------------
51 ---------
61 -------------------------------------
76 -----------------
80 Buttress with a copy of the SoC time, this counter maintains the up-to-date time
90 32-bit virtual address space. The IPU6 has MMU address translation hardware to
94 IPU6 driver. The IPU6 driver sets the level-1 page table base address to MMU
98 page table entries for each DMA operation and invalidate the MMU TLB after each
106 component includes 3 entries - manifest, metadata and module data. Manifest and
[all …]
/linux-6.14.4/arch/sh/kernel/cpu/
Dinit.c1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2002 - 2009 Paul Mundt
39 * Generic wrapper for command line arguments to disable on-chip
85 * Disable support for slottable sleep instruction, non-nop in expmask_init()
87 * the memory-mapped cache array. in expmask_init()
98 /* 2nd-level cache init */
104 * Generic first-level cache init
115 * At this point we don't know whether the cache is enabled or not - a in cache_init()
120 * => before re-initialising the cache, we must do a purge of the whole in cache_init()
123 * - RPC in cache_init()
[all …]
/linux-6.14.4/arch/x86/mm/
Dpgtable.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <asm/tlb.h>
11 phys_addr_t physical_mask __ro_after_init = (1ULL << __PHYSICAL_MASK_SHIFT) - 1;
24 void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table) in paravirt_tlb_remove_table() argument
29 tlb_remove_page(tlb, ptdesc_page(ptdesc)); in paravirt_tlb_remove_table()
33 void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table) in paravirt_tlb_remove_table() argument
35 tlb_remove_table(tlb, table); in paravirt_tlb_remove_table()
50 return -EINVAL; in setup_userpte()
59 return -EINVAL; in setup_userpte()
64 void ___pte_free_tlb(struct mmu_gather *tlb, struct page *pte) in ___pte_free_tlb() argument
[all …]
Dtlb.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <asm/nospec-branch.h>
23 #include <asm/tlb.h>
38 * TLB flushing, formerly SMP-only
69 * Instead we have a small per-cpu array of ASIDs and cache the last few mm's
76 * ASID - [0, TLB_NR_DYN_ASIDS-1]
79 * kPCID - [1, TLB_NR_DYN_ASIDS]
83 * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
100 #define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
103 * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account
[all …]

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