Lines Matching +full:d +full:- +full:tlb +full:- +full:sets
1 // SPDX-License-Identifier: GPL-2.0
6 #include <asm/tlb.h>
11 phys_addr_t physical_mask __ro_after_init = (1ULL << __PHYSICAL_MASK_SHIFT) - 1;
24 void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table) in paravirt_tlb_remove_table() argument
29 tlb_remove_page(tlb, ptdesc_page(ptdesc)); in paravirt_tlb_remove_table()
33 void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table) in paravirt_tlb_remove_table() argument
35 tlb_remove_table(tlb, table); in paravirt_tlb_remove_table()
50 return -EINVAL; in setup_userpte()
59 return -EINVAL; in setup_userpte()
64 void ___pte_free_tlb(struct mmu_gather *tlb, struct page *pte) in ___pte_free_tlb() argument
67 paravirt_tlb_remove_table(tlb, page_ptdesc(pte)); in ___pte_free_tlb()
71 void ___pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd) in ___pmd_free_tlb() argument
75 * NOTE! For PAE, any changes to the top page-directory-pointer-table in ___pmd_free_tlb()
79 tlb->need_flush_all = 1; in ___pmd_free_tlb()
81 paravirt_tlb_remove_table(tlb, virt_to_ptdesc(pmd)); in ___pmd_free_tlb()
85 void ___pud_free_tlb(struct mmu_gather *tlb, pud_t *pud) in ___pud_free_tlb() argument
88 paravirt_tlb_remove_table(tlb, virt_to_ptdesc(pud)); in ___pud_free_tlb()
92 void ___p4d_free_tlb(struct mmu_gather *tlb, p4d_t *p4d) in ___p4d_free_tlb() argument
95 paravirt_tlb_remove_table(tlb, virt_to_ptdesc(p4d)); in ___p4d_free_tlb()
105 list_add(&ptdesc->pt_list, &pgd_list); in pgd_list_add()
112 list_del(&ptdesc->pt_list); in pgd_list_del()
123 virt_to_ptdesc(pgd)->pt_mm = mm; in pgd_set_mm()
128 return page_ptdesc(page)->pt_mm; in pgd_page_get_mm()
134 ptes in non-PAE, or shared PMD in PAE), then just copy the in pgd_ctor()
162 * List of all pgd's needed for non-PAE so it can invalidate entries
165 * tactic would be needed. This is essentially codepath-based locking
169 * -- nyc
174 * In PAE mode, we need to do a cr3 reload (=tlb flush) when
175 * updating the top-level pagetable entries to guarantee the
177 * all 4 top-level entries are used almost immediately in a
178 * new process's life, we just pre-populate them here.
188 * We allocate separate PMDs for the kernel part of the user page-table
189 * when PTI is enabled. We need them to map the per-process LDT into the
190 * user-space page-table.
205 * According to Intel App note "TLBs, Paging-Structure Caches, in pud_populate()
206 * and Their Invalidation", April 2007, document 317080-001, in pud_populate()
208 * TLB via cr3 if the top-level pgd is changed... in pud_populate()
214 /* No need to prepopulate any pagetable entries in non-PAE modes. */
267 return -ENOMEM; in preallocate_pmds()
393 * page for pgd. We are able to just allocate a 32-byte for pgd. in pgtable_cache_init()
394 * During boot time, we create a 32-byte slab for pgd table allocation. in pgtable_cache_init()
411 * a 32-byte slab for pgd to save memory space. in _pgd_alloc()
447 mm->pgd = pgd; in pgd_alloc()
461 * Make sure that pre-populating the pmds is atomic with in pgd_alloc()
529 * We had a write-protection fault here and changed the pmd in pmdp_set_access_flags()
530 * to to more permissive. No need to flush the TLB for that, in pmdp_set_access_flags()
532 * worst-case we'll generate a spurious fault. in pmdp_set_access_flags()
549 * We had a write-protection fault here and changed the pud in pudp_set_access_flags()
550 * to to more permissive. No need to flush the TLB for that, in pudp_set_access_flags()
552 * worst-case we'll generate a spurious fault. in pudp_set_access_flags()
567 (unsigned long *) &ptep->pte); in ptep_test_and_clear_young()
604 * On x86 CPUs, clearing the accessed bit without a TLB flush in ptep_clear_flush_young()
609 * So as a performance optimization don't flush the TLB when in ptep_clear_flush_young()
660 * reserve_top_address - reserves a hole in the top of kernel address space
661 * @reserve - size of hole to reserve
670 __FIXADDR_TOP = round_down(-reserve, 1 << PMD_SHIFT) - PAGE_SIZE; in reserve_top_address()
672 -reserve, __FIXADDR_TOP + PAGE_SIZE); in reserve_top_address()
711 * p4d_set_huge - setup kernel P4D mapping
713 * No 512GB pages yet -- always return 0
721 * p4d_clear_huge - clear kernel P4D mapping when it is set
723 * No 512GB pages yet -- always return 0
731 * pud_set_huge - setup kernel PUD mapping
734 * function sets up a huge page only if the complete range has the same MTRR
737 * Callers should try to decrease page size (1GB -> 2MB -> 4K) if the bigger
750 /* Bail out if we are we on a populated non-leaf entry: */ in pud_set_huge()
762 * pmd_set_huge - setup kernel PMD mapping
774 …pr_warn_once("%s: Cannot satisfy [mem %#010llx-%#010llx] with a huge-page mapping due to MTRR over… in pmd_set_huge()
779 /* Bail out if we are we on a populated non-leaf entry: */ in pmd_set_huge()
791 * pud_clear_huge - clear kernel PUD mapping when it is set
806 * pmd_clear_huge - clear kernel PMD mapping when it is set
822 * pud_free_pmd_page - Clear pud entry and free pmd page.
826 * Context: The pud range has been unmapped and TLB purged.
850 /* INVLPG to clear all paging-structure caches */ in pud_free_pmd_page()
851 flush_tlb_kernel_range(addr, addr + PAGE_SIZE-1); in pud_free_pmd_page()
869 * pmd_free_pte_page - Clear pmd entry and free pte page.
873 * Context: The pmd range has been unmapped and TLB purged.
883 /* INVLPG to clear all paging-structure caches */ in pmd_free_pte_page()
884 flush_tlb_kernel_range(addr, addr + PAGE_SIZE-1); in pmd_free_pte_page()
894 * Disable free page handling on x86-PAE. This assures that ioremap()
895 * does not update sync'd pmd entries. See vmalloc_sync_one().
907 if (vma->vm_flags & VM_SHADOW_STACK) in pte_mkwrite()
917 if (vma->vm_flags & VM_SHADOW_STACK) in pmd_mkwrite()
934 VM_WARN_ON_ONCE(!(vma->vm_flags & VM_SHADOW_STACK) && in arch_check_zapped_pte()
941 VM_WARN_ON_ONCE(!(vma->vm_flags & VM_SHADOW_STACK) && in arch_check_zapped_pmd()
948 VM_WARN_ON_ONCE(!(vma->vm_flags & VM_SHADOW_STACK) && pud_shstk(pud)); in arch_check_zapped_pud()