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Searched refs:DMA2_Stream1_BASE (Results 1 – 24 of 24) sorted by relevance

/btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Device/ST/STM32F4xx/Include/
H A Dstm32f410rx.h630 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
698 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f410tx.h623 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
688 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f410cx.h630 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
698 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f401xe.h712 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
800 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f401xc.h712 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
800 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f411xe.h714 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
803 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f412cx.h886 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
992 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f405xx.h909 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
1024 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f415xx.h977 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
1095 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f412zx.h935 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
1049 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f407xx.h1005 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
1126 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f412vx.h935 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
1047 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f413xx.h1039 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
1178 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f423xx.h1073 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
1213 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f412rx.h932 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
1043 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f417xx.h1073 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
1197 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f446xx.h1022 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
1144 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f427xx.h1085 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
1218 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f437xx.h1157 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
1293 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f429xx.h1138 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
1274 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f439xx.h1208 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
1347 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f469xx.h1229 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
1365 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
H A Dstm32f479xx.h1299 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
1438 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
/btstack/port/stm32-f4discovery-cc256x/Drivers/CMSIS/Device/ST/STM32F4xx/Include/
H A Dstm32f407xx.h1021 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) macro
1142 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)