Home
last modified time | relevance | path

Searched refs:ADC_CSR_AWD1_Pos (Results 1 – 24 of 24) sorted by relevance

/btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Device/ST/STM32F4xx/Include/
H A Dstm32f410rx.h1211 #define ADC_CSR_AWD1_Pos (0U) macro
1212 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f410tx.h1201 #define ADC_CSR_AWD1_Pos (0U) macro
1202 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f410cx.h1211 #define ADC_CSR_AWD1_Pos (0U) macro
1212 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f401xe.h1313 #define ADC_CSR_AWD1_Pos (0U) macro
1314 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f401xc.h1313 #define ADC_CSR_AWD1_Pos (0U) macro
1314 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f411xe.h1316 #define ADC_CSR_AWD1_Pos (0U) macro
1317 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f412cx.h1506 #define ADC_CSR_AWD1_Pos (0U) macro
1507 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f405xx.h1547 #define ADC_CSR_AWD1_Pos (0U) macro
1548 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f415xx.h1621 #define ADC_CSR_AWD1_Pos (0U) macro
1622 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f412zx.h1566 #define ADC_CSR_AWD1_Pos (0U) macro
1567 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f407xx.h1651 #define ADC_CSR_AWD1_Pos (0U) macro
1652 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f412vx.h1564 #define ADC_CSR_AWD1_Pos (0U) macro
1565 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f413xx.h1695 #define ADC_CSR_AWD1_Pos (0U) macro
1696 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f423xx.h1731 #define ADC_CSR_AWD1_Pos (0U) macro
1732 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f412rx.h1560 #define ADC_CSR_AWD1_Pos (0U) macro
1561 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f417xx.h1725 #define ADC_CSR_AWD1_Pos (0U) macro
1726 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f446xx.h1668 #define ADC_CSR_AWD1_Pos (0U) macro
1669 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f427xx.h1745 #define ADC_CSR_AWD1_Pos (0U) macro
1746 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f437xx.h1823 #define ADC_CSR_AWD1_Pos (0U) macro
1824 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f429xx.h1801 #define ADC_CSR_AWD1_Pos (0U) macro
1802 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f439xx.h1877 #define ADC_CSR_AWD1_Pos (0U) macro
1878 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f469xx.h1892 #define ADC_CSR_AWD1_Pos (0U) macro
1893 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
H A Dstm32f479xx.h1968 #define ADC_CSR_AWD1_Pos (0U) macro
1969 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
/btstack/port/stm32-f4discovery-cc256x/Drivers/CMSIS/Device/ST/STM32F4xx/Include/
H A Dstm32f407xx.h1667 #define ADC_CSR_AWD1_Pos (0U) macro
1668 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */