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/linux-6.14.4/Documentation/devicetree/bindings/usb/
Dnvidia,tegra124-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
20 - description: NVIDIA Tegra124
21 const: nvidia,tegra124-xusb
23 - description: NVIDIA Tegra132
[all …]
Dnvidia,tegra210-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
18 const: nvidia,tegra210-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
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Dmediatek,mtk-xhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek USB3 xHCI
11 - Chunfeng Yun <[email protected]>
14 - $ref: usb-xhci.yaml
19 case 2: supports dual-role mode, and the host is based on xHCI driver.
25 - enum:
26 - mediatek,mt2701-xhci
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Dnvidia,tegra194-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
18 const: nvidia,tegra194-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
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Dnvidia,tegra186-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra186-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
18 const: nvidia,tegra186-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
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Dsnps,dwc3-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare USB3 Controller common properties
10 - Felipe Balbi <[email protected]>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
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Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek USB3 DRD Controller
11 - Chunfeng Yun <[email protected]>
14 - $ref: usb-drd.yaml
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
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Dnvidia,tegra-xudc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Nagarjuna Kristam <[email protected]>
15 - JC Kuo <[email protected]>
16 - Thierry Reding <[email protected]>
21 - enum:
22 - nvidia,tegra210-xudc # For Tegra210
23 - nvidia,tegra186-xudc # For Tegra186
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Drenesas,usb3-peri.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/usb/renesas,usb3-peri.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yoshihiro Shimoda <[email protected]>
15 - items:
16 - enum:
17 - renesas,r8a774a1-usb3-peri # RZ/G2M
18 - renesas,r8a774b1-usb3-peri # RZ/G2N
19 - renesas,r8a774c0-usb3-peri # RZ/G2E
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Drockchip,rk3399-dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <[email protected]>
14 const: rockchip,rk3399-dwc3
16 '#address-cells':
19 '#size-cells':
26 - description:
28 - description:
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Dsnps,dwc3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare USB3 Controller
10 - Felipe Balbi <[email protected]>
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: snps,dwc3-common.yaml#
24 - const: snps,dwc3
25 - const: synopsys,dwc3
38 interrupt-names:
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Ddwc3-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mubin Sayyed <[email protected]>
11 - Radhey Shyam Pandey <[email protected]>
16 - enum:
17 - xlnx,zynqmp-dwc3
18 - xlnx,versal-dwc3
22 "#address-cells":
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Drealtek,rtd-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/realtek,rtd-dwc3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Stanley Chang <[email protected]>
15 and USB 3.0 in host or dual-role mode.
20 - enum:
21 - realtek,rtd1295-dwc3
22 - realtek,rtd1315e-dwc3
23 - realtek,rtd1319-dwc3
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/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
Dsocionext,uniphier-usb3ss-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
11 USB3 controller implemented on Socionext UniPhier SoCs.
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <[email protected]>
21 - socionext,uniphier-pro4-usb3-ssphy
[all …]
Dqcom,usb-ss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bryan O'Donoghue <[email protected]>
18 - qcom,usb-ss-28nm-phy
23 "#phy-cells":
28 - description: rpmcc clock
29 - description: PHY AHB clock
30 - description: SuperSpeed pipe clock
[all …]
/linux-6.14.4/drivers/usb/cdns3/
DKconfig8 dual-role controller.
9 It supports: dual-role switch, Host-only, and Peripheral-only.
17 tristate "Cadence USB3 Dual-Role Controller"
20 Say Y here if your system has a Cadence USB3 dual-role controller.
21 It supports: dual-role switch, Host-only, and Peripheral-only.
30 bool "Cadence USB3 device controller"
34 Cadence USBSS-DEV driver.
36 This controller supports FF, HS and SS mode. It doesn't support
40 bool "Cadence USB3 host controller"
51 tristate "Cadence USB3 support on PCIe-based platforms"
[all …]
Dcdns3-gadget.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2017-2018 NXP
15 #include <linux/dma-direction.h>
18 * USBSS-DEV register interface.
23 * struct cdns3_usb_regs - device controller registers.
53 * @buf_addr: Address for On-chip Buffer operations.
54 * @buf_data: Data for On-chip Buffer operations.
55 * @buf_ctrl: On-chip Buffer Access Control.
123 /* USB_CONF - bitmasks */
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/linux-6.14.4/drivers/phy/socionext/
Dphy-uniphier-usb3ss.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-uniphier-usb3ss.c - SS-PHY driver for Socionext UniPhier USB3 controller
4 * Copyright 2015-2018 Socionext Inc.
73 writel(data, priv->base + SSPHY_TESTI); in uniphier_u3ssphy_testio_write()
74 readl(priv->base + SSPHY_TESTO); in uniphier_u3ssphy_testio_write()
75 readl(priv->base + SSPHY_TESTO); in uniphier_u3ssphy_testio_write()
82 u8 field_mask = GENMASK(p->field.msb, p->field.lsb); in uniphier_u3ssphy_set_param()
87 val |= FIELD_PREP(TESTI_ADR_MASK, p->field.reg_no); in uniphier_u3ssphy_set_param()
89 val = readl(priv->base + SSPHY_TESTO) & TESTO_DAT_MASK; in uniphier_u3ssphy_set_param()
93 data = field_mask & (p->value << p->field.lsb); in uniphier_u3ssphy_set_param()
[all …]
/linux-6.14.4/arch/arm/boot/dts/nvidia/
Dtegra124-nyan.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/thermal/thermal.h>
14 stdout-path = "serial0:115200n8";
20 * missing a unit-address. However, the bootloader on these Chromebook
22 * Adding the unit-address causes the bootloader to create a /memory
34 /delete-node/ memory@80000000;
40 vdd-supply = <&vdd_3v3_hdmi>;
41 pll-supply = <&vdd_hdmi_pll>;
42 hdmi-supply = <&vdd_5v0_hdmi>;
[all …]
Dtegra124-venice2.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
29 vdd-supply = <&vdd_3v3_hdmi>;
30 pll-supply = <&vdd_hdmi_pll>;
31 hdmi-supply = <&vdd_5v0_hdmi>;
33 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
34 nvidia,hpd-gpio =
41 avdd-io-hdmi-dp-supply = <&vdd_1v05_run>;
[all …]
/linux-6.14.4/drivers/phy/qualcomm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
69 with USB3 and DisplayPort controllers on Qualcomm chips.
103 with USB3 controllers on Qualcomm chips.
111 PHY transceivers working only in USB3 mode on Qualcomm chips. This
124 controllers on Qualcomm chips. This driver supports the high-speed
133 Enable support for the USB high-speed SNPS eUSB2 phy on Qualcomm
142 Enable support for the USB high-speed SNPS eUSB2 repeater on Qualcomm
160 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
163 Support for the USB high-speed ULPI compliant phy on Qualcomm
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/connector/
Dusb-connector.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/connector/usb-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <[email protected]>
20 - enum:
21 - usb-a-connector
22 - usb-b-connector
23 - usb-c-connector
25 - items:
[all …]
/linux-6.14.4/drivers/usb/host/
Dxhci-tegra.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
11 #include <linux/dma-mapping.h>
237 } usb2, ulpi, hsic, usb3; member
322 return readl(tegra->fpci_base + offset); in fpci_readl()
328 writel(value, tegra->fpci_base + offset); in fpci_writel()
333 return readl(tegra->ipfs_base + offset); in ipfs_readl()
339 writel(value, tegra->ipfs_base + offset); in ipfs_writel()
344 return readl(tegra->bar2_base + offset); in bar2_readl()
350 writel(value, tegra->bar2_base + offset); in bar2_writel()
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