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/linux-6.14.4/arch/arm/boot/dts/qcom/
Dqcom-apq8064-pins.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 sdcc1_default_state: sdcc1-default-state {
5 clk-pins {
7 drive-strength = <16>;
8 bias-disable;
11 cmd-pins {
13 drive-strength = <10>;
14 bias-pull-up;
17 data-pins {
19 drive-strength = <10>;
[all …]
/linux-6.14.4/drivers/tty/serial/8250/
D8250_mtk.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <linux/dma-mapping.h>
28 #define MTK_UART_RATE_FIX 0x0d /* UART Rate Fix Register */
94 struct uart_8250_dma *dma = up->dma; in mtk8250_dma_rx_complete()
95 struct mtk8250_data *data = up->port.private_data; in mtk8250_dma_rx_complete()
96 struct tty_port *tty_port = &up->port.state->port; in mtk8250_dma_rx_complete()
97 struct dma_tx_state state; in mtk8250_dma_rx_complete() local
102 if (data->rx_status == DMA_RX_SHUTDOWN) in mtk8250_dma_rx_complete()
105 uart_port_lock_irqsave(&up->port, &flags); in mtk8250_dma_rx_complete()
107 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); in mtk8250_dma_rx_complete()
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D8250_pxa.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/tty/serial/8250/8250_pxa.c -- driver for PXA on-board UARTS
37 serial8250_suspend_port(data->line); in serial_pxa_suspend()
46 serial8250_resume_port(data->line); in serial_pxa_resume()
56 { .compatible = "mrvl,pxa-uart", },
57 { .compatible = "mrvl,mmp-uart", },
62 /* Uart divisor latch write */
79 static void serial_pxa_pm(struct uart_port *port, unsigned int state, in serial_pxa_pm() argument
82 struct pxa8250_data *data = port->private_data; in serial_pxa_pm()
84 if (!state) in serial_pxa_pm()
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D8250_dw.c1 // SPDX-License-Identifier: GPL-2.0+
10 * raised, the LCR needs to be rewritten and the uart status register read.
34 #define DW_UART_USR 0x1f /* UART Status Register */
37 #define OCTEON_UART_USR 0x27 /* UART Status Register */
99 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_modify_msr()
103 value |= d->msr_mask_on; in dw8250_modify_msr()
104 value &= ~d->msr_mask_off; in dw8250_modify_msr()
122 if (up->fcr & UART_FCR_ENABLE_FIFO) { in dw8250_force_idle()
123 lsr = p->serial_in(p, UART_LSR); in dw8250_force_idle()
128 (void)p->serial_in(p, UART_RX); in dw8250_force_idle()
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/linux-6.14.4/arch/mips/kernel/
Dcps-vec-ns16550.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #include <asm/asm-offsets.h>
32 * _mips_cps_putc() - write a character to the UART
34 * @t9: UART base address
45 * _mips_cps_puts() - write a string to the UART
46 * @a0: pointer to NULL-terminated ASCII string
47 * @t9: UART base address
49 * Write a null-terminated ASCII string to the UART.
65 * _mips_cps_putx4 - write a 4b hex value to the UART
66 * @a0: the 4b value to write to the UART
[all …]
/linux-6.14.4/drivers/tty/serial/
Darc_uart.c1 // SPDX-License-Identifier: GPL-2.0
3 * ARC On-Chip(fpga) UART Driver
5 * Copyright (C) 2010-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Decoupled the driver from arch/arc
10 * +Using early_platform_xxx() for early console (thx to mach-shmobile/xxx)
13 * -Is uart_tx_stopped() not done in tty write path as it has already been
17 * -New Serial Core based ARC UART driver
18 * -Derived largely from blackfin driver albiet with some major tweaks
21 * -check if sysreq works
37 * ARC UART Hardware Specs
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Dtimbuart.c1 // SPDX-License-Identifier: GPL-2.0
3 * timbuart.c timberdale FPGA UART driver
8 * Timberdale FPGA UART
42 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; in timbuart_stop_rx()
43 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_rx()
49 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; in timbuart_stop_tx()
50 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_tx()
55 struct timbuart_port *uart = in timbuart_start_tx() local
58 /* do not transfer anything here -> fire off the tasklet */ in timbuart_start_tx()
59 tasklet_schedule(&uart->tasklet); in timbuart_start_tx()
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Dmen_z135_uart.c1 // SPDX-License-Identifier: GPL-2.0
3 * MEN 16z135 High Speed UART
104 MODULE_PARM_DESC(txlvl, "TX IRQ trigger level 0-7, default 5 (128 byte)");
108 MODULE_PARM_DESC(rxlvl, "RX IRQ trigger level 0-7, default 6 (256 byte)");
131 * men_z135_reg_set() - Set value in register
132 * @uart: The UART port
136 static inline void men_z135_reg_set(struct men_z135_port *uart, in men_z135_reg_set() argument
139 struct uart_port *port = &uart->port; in men_z135_reg_set()
143 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_set()
145 reg = ioread32(port->membase + addr); in men_z135_reg_set()
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Dsamsung_tty.c1 // SPDX-License-Identifier: GPL-2.0
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
12 * UERSTAT register in the UART blocks, and keeps marking some of the
21 * BJD, 04-Nov-2004
28 #include <linux/dma-mapping.h>
48 /* UART name and device definitions */
91 /* uart port features */
165 #define portaddr(port, reg) ((port)->membase + (reg))
167 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
171 switch (port->iotype) { in rd_reg()
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Dmsm_serial.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/dma-mapping.h>
178 struct uart_port uart; member
192 return container_of(up, struct msm_port, uart); in to_msm_port()
198 writel_relaxed(val, port->membase + off); in msm_write()
204 return readl_relaxed(port->membase + off); in msm_read()
216 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxo()
228 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxoby4()
239 if (msm_port->is_uartdm) in msm_serial_set_mnd_regs()
242 if (port->uartclk == 19200000) in msm_serial_set_mnd_regs()
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Dserial_txx9.c1 // SPDX-License-Identifier: GPL-2.0
10 * Copyright (C) 2000-2002 Toshiba Corporation
161 switch (up->iotype) { in sio_in()
163 return __raw_readl(up->membase + offset); in sio_in()
165 return inl(up->iobase + offset); in sio_in()
172 switch (up->iotype) { in sio_out()
174 __raw_writel(value, up->membase + offset); in sio_out()
177 outl(value, up->iobase + offset); in sio_out()
221 up->read_status_mask &= ~TXX9_SIDISR_RDIS; in serial_txx9_stop_rx()
232 while ((sio_in(up, TXX9_SIFCR) & TXX9_SIFCR_SWRST) && --tmout) in serial_txx9_initialize()
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Dxilinx_uartps.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence UART driver (found in Xilinx Zynq)
5 * Copyright (c) 2011 - 2014 Xilinx, Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
42 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
47 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
49 /* Register offsets for the UART. */
90 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
181 #define CDNS_UART_SR_TACTIVE 0x00000800 /* TX state machine active */
190 * struct cdns_uart - device data
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Datmel_serial.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/clk-provider.h>
24 #include <linux/dma-mapping.h>
62 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
64 * UART. */
71 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
113 struct uart_port uart; /* uart */ member
114 struct clk *clk; /* uart clock */
115 struct clk *gclk; /* uart generic clock */
167 bool hd_start_rx; /* can start RX during half-duplex operation */
[all …]
Dpic32_uart.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Sorin-Andrei Pistirica <[email protected]>
26 #include <asm/mach-pic32/pic32.h>
28 /* UART name and device definitions */
29 #define PIC32_DEV_NAME "pic32-uart"
43 /* struct pic32_sport - pic32 serial port descriptor
44 * @port: uart port descriptor
82 __raw_writel(val, sport->port.membase + reg); in pic32_uart_writel()
87 return __raw_readl(sport->port.membase + reg); in pic32_uart_readl()
90 /* pic32 uart mode register bits */
[all …]
/linux-6.14.4/include/linux/
Dserial_core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
25 ((port)->cons && (port)->cons->index == (port)->line)
37 * struct uart_ops -- interface between serial_core and the driver
55 * This function sets the modem control lines for @port to the state
58 * - %TIOCM_RTS RTS signal.
59 * - %TIOCM_DTR DTR signal.
60 * - %TIOCM_OUT1 OUT1 signal.
61 * - %TIOCM_OUT2 OUT2 signal.
62 * - %TIOCM_LOOP Set the port into loopback mode.
68 * Locking: @port->lock taken.
[all …]
/linux-6.14.4/drivers/acpi/
Dspcr.c1 // SPDX-License-Identifier: GPL-2.0-only
18 * TXFE == 0 instead of BUSY == 1. This may not be suitable for all UART
26 * Some Qualcomm Datacenter Technologies SoCs have a defective UART BUSY bit.
32 if (memcmp(h->oem_id, "QCOM ", ACPI_OEM_ID_SIZE)) in qdf2400_erratum_44_present()
35 if (!memcmp(h->oem_table_id, "QDF2432 ", ACPI_OEM_TABLE_ID_SIZE)) in qdf2400_erratum_44_present()
38 if (!memcmp(h->oem_table_id, "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) && in qdf2400_erratum_44_present()
39 h->oem_revision == 1) in qdf2400_erratum_44_present()
46 * APM X-Gene v1 and v2 UART hardware is an 16550 like device but has its
47 * register aligned to 32-bit. In addition, the BIOS also encoded the
54 if (tb->interface_type != ACPI_DBG2_16550_COMPATIBLE) in xgene_8250_erratum_present()
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/linux-6.14.4/drivers/usb/serial/
Dmct_u232.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Definitions for MCT (Magic Control Technology) USB-RS232 Converter Driver
7 * This driver is for the device MCT USB-RS232 Converter (25 pin, Model No.
8 * U232-P25) from Magic Control Technology Corp. (there is also a 9 pin
9 * Model No. U232-P9). See http://www.mct.com.tw/products/product_us232.html
11 * of this file. This device was used in the Dlink DSB-S25.
24 /* U232-P25, Sitecom */
27 /* DU-H3SP USB BAY hub */
28 #define MCT_U232_DU_H3SP_PID 0x0200 /* D-Link DU-H3SP USB BAY */
30 /* Belkin badge the MCT U232-P9 as the F5U109 */
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Dwhiteheat.h1 /* SPDX-License-Identifier: GPL-2.0+ */
9 * Greg Kroah-Hartman ([email protected])
11 * See Documentation/usb/usb-serial.rst for more information on using this
29 #define WHITEHEAT_PURGE 9 /* clear the UART fifos */
30 #define WHITEHEAT_GET_DTR_RTS 10 /* get the state of DTR and RTS
90 __le32 baud; /* any value 7 - 460800, firmware calculates
117 __u8 state; /* 0/1 turns signal off/on */ member
131 * Type DATA: 0x00 - 0xff
132 * Type IDATA: 0x80 - 0xff
133 * Type BDATA: 0x20 - 0x2f
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/linux-6.14.4/arch/mips/include/asm/sn/sn0/
Dhubmd.h8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
38 #define MD_FANDOP_CAC_STAT 0x200028 /* Fetch-and-op cache status */
64 #define MD_UREG0_0 0x220000 /* uController/UART 0 register */
65 #define MD_UREG0_1 0x220008 /* uController/UART 0 register */
66 #define MD_UREG0_2 0x220010 /* uController/UART 0 register */
67 #define MD_UREG0_3 0x220018 /* uController/UART 0 register */
68 #define MD_UREG0_4 0x220020 /* uController/UART 0 register */
69 #define MD_UREG0_5 0x220028 /* uController/UART 0 register */
70 #define MD_UREG0_6 0x220030 /* uController/UART 0 register */
71 #define MD_UREG0_7 0x220038 /* uController/UART 0 register */
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/linux-6.14.4/Documentation/devicetree/bindings/serial/
Dmicrochip,pic32-uart.txt1 * Microchip Universal Asynchronous Receiver Transmitter (UART)
4 - compatible: Should be "microchip,pic32mzda-uart"
5 - reg: Should contain registers location and length
6 - interrupts: Should contain interrupt
7 - clocks: Phandle to the clock.
8 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
9 - pinctrl-names: A pinctrl state names "default" must be defined.
10 - pinctrl-0: Phandle referencing pin configuration of the UART peripheral.
11 See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
14 - cts-gpios: CTS pin for UART
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/linux-6.14.4/Documentation/devicetree/bindings/net/bluetooth/
Dmediatek,bluetooth.txt1 MediaTek UART based Bluetooth Devices
4 This device is a serial attached device to UART device and thus it must be a
5 child node of the serial node with UART.
13 - compatible: Must be
14 "mediatek,mt7663u-bluetooth": for MT7663U device
15 "mediatek,mt7668u-bluetooth": for MT7668U device
16 - vcc-supply: Main voltage regulator
21 - pinctrl-names: Should be "default", "runtime"
22 - pinctrl-0: Should contain UART RXD low when the device is powered up to
24 - pinctrl-1: Should contain UART mode pin ctrl
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/linux-6.14.4/arch/arm/include/debug/
Dtegra.S1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2011-2012 NVIDIA CORPORATION. All Rights Reserved.
12 * Portions based on mach-omap2's debug-macro.S
13 * Copyright (C) 1994-1999 Russell King
40 * Must be section-aligned since a section mapping is used early on.
41 * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[].
45 #define checkuart(rp, rv, lhu, bit, uart) \ argument
50 /* Test UART's reset bit */ \
52 /* If set, can't use UART; jump to save no UART */ \
58 /* Test UART's clock enable bit */ \
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/linux-6.14.4/arch/arm64/boot/dts/exynos/google/
Dgs101.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2019-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <[email protected]>
9 #include <dt-bindings/clock/google,gs101.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/soc/samsung,exynos-usi.h>
16 #address-cells = <2>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
[all …]
/linux-6.14.4/drivers/extcon/
Dextcon-max8997.c1 // SPDX-License-Identifier: GPL-2.0+
3 // extcon-max8997.c - MAX8997 extcon driver to support MAX8997 MUIC
8 #include <linux/devm-helpers.h>
18 #include <linux/mfd/max8997-private.h>
19 #include <linux/extcon-provider.h>
22 #define DEV_NAME "max8997-muic"
39 { MAX8997_MUICIRQ_ADCError, "muic-ADCERROR" },
40 { MAX8997_MUICIRQ_ADCLow, "muic-ADCLOW" },
41 { MAX8997_MUICIRQ_ADC, "muic-ADC" },
42 { MAX8997_MUICIRQ_VBVolt, "muic-VBVOLT" },
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/linux-6.14.4/Documentation/devicetree/bindings/mfd/
Daspeed-lpc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Jeffery <[email protected]>
12 - Chia-Wei Wang <[email protected]>
15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
21 The LPC controller is represented as a multi-function device to account for the
27 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
34 Additionally the state of the LPC controller influences the pinmux
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