Lines Matching +full:uart +full:- +full:state
8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
38 #define MD_FANDOP_CAC_STAT 0x200028 /* Fetch-and-op cache status */
64 #define MD_UREG0_0 0x220000 /* uController/UART 0 register */
65 #define MD_UREG0_1 0x220008 /* uController/UART 0 register */
66 #define MD_UREG0_2 0x220010 /* uController/UART 0 register */
67 #define MD_UREG0_3 0x220018 /* uController/UART 0 register */
68 #define MD_UREG0_4 0x220020 /* uController/UART 0 register */
69 #define MD_UREG0_5 0x220028 /* uController/UART 0 register */
70 #define MD_UREG0_6 0x220030 /* uController/UART 0 register */
71 #define MD_UREG0_7 0x220038 /* uController/UART 0 register */
73 #define MD_SLOTID_USTAT 0x220048 /* Hub slot ID & UART/uCtlr status */
74 #define MD_LED0 0x220050 /* Eight-bit LED for CPU A */
75 #define MD_LED1 0x220058 /* Eight-bit LED for CPU B */
77 #define MD_UREG1_0 0x220080 /* uController/UART 1 register */
78 #define MD_UREG1_1 0x220088 /* uController/UART 1 register */
79 #define MD_UREG1_2 0x220090 /* uController/UART 1 register */
80 #define MD_UREG1_3 0x220098 /* uController/UART 1 register */
81 #define MD_UREG1_4 0x2200a0 /* uController/UART 1 register */
82 #define MD_UREG1_5 0x2200a8 /* uController/UART 1 register */
83 #define MD_UREG1_6 0x2200b0 /* uController/UART 1 register */
84 #define MD_UREG1_7 0x2200b8 /* uController/UART 1 register */
85 #define MD_UREG1_8 0x2200c0 /* uController/UART 1 register */
86 #define MD_UREG1_9 0x2200c8 /* uController/UART 1 register */
87 #define MD_UREG1_10 0x2200d0 /* uController/UART 1 register */
88 #define MD_UREG1_11 0x2200d8 /* uController/UART 1 register */
89 #define MD_UREG1_12 0x2200e0 /* uController/UART 1 register */
90 #define MD_UREG1_13 0x2200e8 /* uController/UART 1 register */
91 #define MD_UREG1_14 0x2200f0 /* uController/UART 1 register */
92 #define MD_UREG1_15 0x2200f8 /* uController/UART 1 register */
270 * various MD registers. For multi-bit registers, we define both
288 * to forcing the ECC to be written as-is instead of recalculated.
296 * as shown, and low and/or high indicates which double-word of the entry.
298 * Format A: STATE = shared, FINE = 1
299 * Format B: STATE = shared, FINE = 0
300 * Format C: STATE != shared (FINE must be 0)
346 * as shown, and low and/or high indicates which double-word of the entry.
348 * Format A: STATE == shared
349 * Format C: STATE != shared
547 rsvd1: 19, /* 60-42: reserved */
548 bad_prot: 3, /* 41-39: encoding, bad access rights*/
549 bad_syn: 7, /* 38-32: bad dir syndrome */
550 rsvd2: 2, /* 31-30: reserved */
551 hspec_addr:27, /* 29-03: bddir space bad entry */
566 rsvd1: 22, /* 61-40: reserved */
567 bad_syn: 8, /* 39-32: bad mem ecc syndrome */
568 address: 29, /* 31-03: bad entry pointer */
583 rsvd1: 2, /* 62-61: reserved */
584 initiator:11, /* 60-50: id of request initiator*/
585 backoff: 2, /* 49-48: backoff control */
586 msg_type: 8, /* 47-40: type of request */
587 access: 2, /* 39-38: access rights of initiator*/
589 dir_state: 4, /* 36-33: state of directory */
591 address: 29, /* 31-03: request address */
592 rsvd2: 2, /* 02-01: reserved */