Lines Matching +full:uart +full:- +full:state
1 // SPDX-License-Identifier: GPL-2.0
3 * ARC On-Chip(fpga) UART Driver
5 * Copyright (C) 2010-2012 Synopsys, Inc. (www.synopsys.com)
8 * -Decoupled the driver from arch/arc
10 * +Using early_platform_xxx() for early console (thx to mach-shmobile/xxx)
13 * -Is uart_tx_stopped() not done in tty write path as it has already been
17 * -New Serial Core based ARC UART driver
18 * -Derived largely from blackfin driver albiet with some major tweaks
21 * -check if sysreq works
37 * ARC UART Hardware Specs
42 * UART Register set (this is not a Standards Compliant IP)
54 /* Bits for UART Status Reg (R/W) */
67 /* Uart bit fiddling helpers: lowest level */
68 #define RBASE(port, reg) (port->membase + reg)
75 /* Uart bit fiddling helpers: API level */
76 #define UART_SET_DATA(uart, val) UART_REG_SET(uart, R_DATA, val) argument
77 #define UART_GET_DATA(uart) UART_REG_GET(uart, R_DATA) argument
79 #define UART_SET_BAUDH(uart, val) UART_REG_SET(uart, R_BAUDH, val) argument
80 #define UART_SET_BAUDL(uart, val) UART_REG_SET(uart, R_BAUDL, val) argument
82 #define UART_CLR_STATUS(uart, val) UART_REG_CLR(uart, R_STS, val) argument
83 #define UART_GET_STATUS(uart) UART_REG_GET(uart, R_STS) argument
85 #define UART_ALL_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, RXIENB|TXIENB) argument
86 #define UART_RX_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, RXIENB) argument
87 #define UART_TX_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, TXIENB) argument
89 #define UART_ALL_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, RXIENB|TXIENB) argument
90 #define UART_RX_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, RXIENB) argument
91 #define UART_TX_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, TXIENB) argument
108 #define DRIVER_NAME "arc-uart"
150 * Driver internal routine, used by both tty(serial core) as well as tx-isr
151 * -Called under spinlock in either cases
152 * -also tty->flow.stopped has already been checked
158 struct tty_port *tport = &port->state->port; in arc_serial_tx_chars()
162 if (unlikely(port->x_char)) { in arc_serial_tx_chars()
163 UART_SET_DATA(port, port->x_char); in arc_serial_tx_chars()
164 port->icount.tx++; in arc_serial_tx_chars()
165 port->x_char = 0; in arc_serial_tx_chars()
178 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in arc_serial_tx_chars()
197 * UART has 4 deep RX-FIFO. Driver's recongnition of this fact in arc_serial_rx_chars()
199 * Upon getting a RX-Intr, such that RX-EMPTY=0, meaning data available, in arc_serial_rx_chars()
201 * RX-EMPTY=1. Multiple chars being avail, with a single Interrupt, in arc_serial_rx_chars()
202 * before RX-EMPTY=0, implies some sort of buffering going on in the in arc_serial_rx_chars()
203 * controller, which is indeed the Rx-FIFO. in arc_serial_rx_chars()
213 port->icount.overrun++; in arc_serial_rx_chars()
219 port->icount.frame++; in arc_serial_rx_chars()
228 port->icount.rx++; in arc_serial_rx_chars()
233 tty_flip_buffer_push(&port->state->port); in arc_serial_rx_chars()
238 * A note on the Interrupt handling state machine of this driver
241 * to keep things simple as well as efficient, it writes to UART in polled
247 * Thus Rx-interrupts are always enabled, while tx-interrupts are by default
252 * -checks-if-tty-buffer-has-char-to-send
253 * -writes-data-to-uart
254 * -enable-tx-intr
256 * Once data bits are pushed out, controller raises the Tx-room-avail-Interrupt.
260 * more char in tty buffer. In case of sending, it re-enables Tx-intr. In case
262 * This is how the transmit state machine is dynamically switched on/off
274 * notifications from the UART Controller. in arc_serial_isr()
287 /* Unconditionally disable further Tx-Interrupts. in arc_serial_isr()
307 * always set, to satify the serial core state machine in arc_serial_get_mctrl()
322 /* ARC UART doesn't support sending Break signal */ in arc_serial_break_ctl()
327 /* Before we hook up the ISR, Disable all UART Interrupts */ in arc_serial_startup()
330 if (request_irq(port->irq, arc_serial_isr, 0, "arc uart rx-tx", port)) { in arc_serial_startup()
331 dev_warn(port->dev, "Unable to attach ARC UART intr\n"); in arc_serial_startup()
332 return -EBUSY; in arc_serial_startup()
343 free_irq(port->irq, port); in arc_serial_shutdown()
350 struct arc_uart_port *uart = to_arc_port(port); in arc_serial_set_termios() local
358 * Formula for ARC UART is: hw-val = ((CLK/(BAUD*4)) -1) in arc_serial_set_termios()
359 * spread over two 8-bit registers in arc_serial_set_termios()
363 hw_val = port->uartclk / (uart->baud * 4) - 1; in arc_serial_set_termios()
377 * UART doesn't support Parity/Hardware Flow Control; in arc_serial_set_termios()
380 new->c_cflag &= ~(CMSPAR|CRTSCTS|CSIZE); in arc_serial_set_termios()
381 new->c_cflag |= CS8; in arc_serial_set_termios()
390 uart_update_timeout(port, new->c_cflag, baud); in arc_serial_set_termios()
397 return port->type == PORT_ARC ? DRIVER_NAME : NULL; in arc_serial_type()
415 if (port->type != PORT_UNKNOWN && ser->type != PORT_ARC) in arc_serial_verify_port()
416 return -EINVAL; in arc_serial_verify_port()
427 port->type = PORT_ARC; in arc_serial_config_port()
484 if (co->index < 0 || co->index >= CONFIG_SERIAL_ARC_NR_PORTS) in arc_serial_console_setup()
485 return -ENODEV; in arc_serial_console_setup()
488 * The uart port backing the console (e.g. ttyARC1) might not have been in arc_serial_console_setup()
491 port = &arc_uart_ports[co->index].port; in arc_serial_console_setup()
492 if (!port->membase) in arc_serial_console_setup()
493 return -ENODEV; in arc_serial_console_setup()
499 * Serial core will call port->ops->set_termios( ) in arc_serial_console_setup()
519 struct uart_port *port = &arc_uart_ports[co->index].port; in arc_serial_console_write()
533 .index = -1,
540 struct earlycon_device *dev = con->data; in arc_early_serial_write()
542 uart_console_write(&dev->port, s, n, arc_serial_console_putchar); in arc_early_serial_write()
548 struct uart_port *port = &dev->port; in arc_early_console_setup()
551 if (!dev->port.membase) in arc_early_console_setup()
552 return -ENODEV; in arc_early_console_setup()
554 hw_val = port->uartclk / (dev->baud * 4) - 1; in arc_early_console_setup()
561 dev->con->write = arc_early_serial_write; in arc_early_console_setup()
564 OF_EARLYCON_DECLARE(arc_uart, "snps,arc-uart", arc_early_console_setup);
570 struct device_node *np = pdev->dev.of_node; in arc_serial_probe()
571 struct arc_uart_port *uart; in arc_serial_probe() local
578 return -ENODEV; in arc_serial_probe()
585 dev_err(&pdev->dev, "serial%d out of range\n", dev_id); in arc_serial_probe()
586 return -EINVAL; in arc_serial_probe()
589 uart = &arc_uart_ports[dev_id]; in arc_serial_probe()
590 port = &uart->port; in arc_serial_probe()
592 if (of_property_read_u32(np, "clock-frequency", &val)) { in arc_serial_probe()
593 dev_err(&pdev->dev, "clock-frequency property NOTset\n"); in arc_serial_probe()
594 return -EINVAL; in arc_serial_probe()
596 port->uartclk = val; in arc_serial_probe()
598 if (of_property_read_u32(np, "current-speed", &val)) { in arc_serial_probe()
599 dev_err(&pdev->dev, "current-speed property NOT set\n"); in arc_serial_probe()
600 return -EINVAL; in arc_serial_probe()
602 uart->baud = val; in arc_serial_probe()
604 port->membase = devm_platform_ioremap_resource(pdev, 0); in arc_serial_probe()
605 if (IS_ERR(port->membase)) { in arc_serial_probe()
606 /* No point of dev_err since UART itself is hosed here */ in arc_serial_probe()
607 return PTR_ERR(port->membase); in arc_serial_probe()
610 port->irq = irq_of_parse_and_map(np, 0); in arc_serial_probe()
612 port->dev = &pdev->dev; in arc_serial_probe()
613 port->iotype = UPIO_MEM; in arc_serial_probe()
614 port->flags = UPF_BOOT_AUTOCONF; in arc_serial_probe()
615 port->line = dev_id; in arc_serial_probe()
616 port->ops = &arc_serial_pops; in arc_serial_probe()
617 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_ARC_CONSOLE); in arc_serial_probe()
619 port->fifosize = ARC_UART_TX_FIFO_SIZE; in arc_serial_probe()
625 port->ignore_status_mask = 0; in arc_serial_probe()
631 { .compatible = "snps,arc-uart" },
671 MODULE_DESCRIPTION("ARC(Synopsys) On-Chip(fpga) serial driver");