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/linux-6.14.4/drivers/tty/serial/8250/
D8250_ingenic.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Lars-Peter Clausen <[email protected]>
6 * Ingenic SoC UART support
26 int fifosize; member
46 return readl(port->membase + (offset << 2)); in early_in()
51 writel(value, port->membase + (offset << 2)); in early_out()
68 uart_console_write(&early_device->port, s, count, in ingenic_early_console_write()
82 prop = fdt_getprop(fdt, offset, "clock-frequency", NULL); in ingenic_early_console_setup_clock()
86 dev->port.uartclk = be32_to_cpup(prop); in ingenic_early_console_setup_clock()
92 struct uart_port *port = &dev->port; in ingenic_earlycon_setup_tail()
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D8250_core.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Universal/legacy driver for 8250/16550-type serial ports
11 * userspace-configurable "phantom" ports
63 * line has been de-asserted.
76 spin_lock(&i->lock); in serial8250_interrupt()
78 l = i->head; in serial8250_interrupt()
84 port = &up->port; in serial8250_interrupt()
86 if (port->handle_irq(port)) { in serial8250_interrupt()
92 l = l->next; in serial8250_interrupt()
94 if (l == i->head && pass_counter++ > PASS_LIMIT) in serial8250_interrupt()
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D8250_of.c1 // SPDX-License-Identifier: GPL-2.0+
53 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2; in npcm_get_divisor()
58 port->get_divisor = npcm_get_divisor; in npcm_setup()
59 port->startup = npcm_startup; in npcm_setup()
72 struct uart_8250_port *port8250 = serial8250_get_port(info->line); in of_platform_serial_clk_notifier_cb()
76 serial8250_update_uartclk(&port8250->port, ndata->new_rate); in of_platform_serial_clk_notifier_cb()
91 struct device *dev = &ofdev->dev; in of_platform_serial_setup()
92 struct device_node *np = dev->of_node; in of_platform_serial_setup()
93 struct uart_port *port = &up->port; in of_platform_serial_setup()
99 pm_runtime_enable(&ofdev->dev); in of_platform_serial_setup()
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D8250_dw.c1 // SPDX-License-Identifier: GPL-2.0+
10 * raised, the LCR needs to be rewritten and the uart status register read.
34 #define DW_UART_USR 0x1f /* UART Status Register */
37 #define OCTEON_UART_USR 0x27 /* UART Status Register */
99 struct dw8250_data *d = to_dw8250_data(p->private_data); in dw8250_modify_msr()
103 value |= d->msr_mask_on; in dw8250_modify_msr()
104 value &= ~d->msr_mask_off; in dw8250_modify_msr()
122 if (up->fcr & UART_FCR_ENABLE_FIFO) { in dw8250_force_idle()
123 lsr = p->serial_in(p, UART_LSR); in dw8250_force_idle()
128 (void)p->serial_in(p, UART_RX); in dw8250_force_idle()
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D8250_pxa.c1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/tty/serial/8250/8250_pxa.c -- driver for PXA on-board UARTS
37 serial8250_suspend_port(data->line); in serial_pxa_suspend()
46 serial8250_resume_port(data->line); in serial_pxa_resume()
56 { .compatible = "mrvl,pxa-uart", },
57 { .compatible = "mrvl,mmp-uart", },
62 /* Uart divisor latch write */
82 struct pxa8250_data *data = port->private_data; in serial_pxa_pm()
85 clk_prepare_enable(data->clk); in serial_pxa_pm()
87 clk_disable_unprepare(data->clk); in serial_pxa_pm()
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D8250_port.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
51 * Here we define the default xmit fifo size used for each type of UART.
244 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
245 * workaround of errata A-008006 which states that tx_loadsz should
257 .name = "Palmchip BK-3103",
315 .name = "Broadcom BCM7271 UART",
324 /* Uart divisor latch read */
334 /* Uart divisor latch write */
344 offset = offset << p->regshift; in hub6_serial_in()
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D8250_bcm2835aux.c1 // SPDX-License-Identifier: GPL-2.0
3 * Serial port driver for BCM2835AUX UART
10 * The bcm2835aux is capable of RTS auto flow-control, but this driver doesn't
38 * struct bcm2835aux_data - driver private data of BCM2835 auxiliary UART
51 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) { in bcm2835aux_rs485_start_tx()
52 struct bcm2835aux_data *data = dev_get_drvdata(up->port.dev); in bcm2835aux_rs485_start_tx()
54 data->cntl &= ~BCM2835_AUX_UART_CNTL_RXEN; in bcm2835aux_rs485_start_tx()
55 serial_out(up, BCM2835_AUX_UART_CNTL, data->cntl); in bcm2835aux_rs485_start_tx()
60 * flags besides RTS. So no need for a read-modify-write. in bcm2835aux_rs485_start_tx()
62 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND) in bcm2835aux_rs485_start_tx()
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/linux-6.14.4/Documentation/devicetree/bindings/serial/
Dsamsung_uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
10 - Krzysztof Kozlowski <[email protected]>
11 - Greg Kroah-Hartman <[email protected]>
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
21 - enum:
22 - apple,s5l-uart
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/linux-6.14.4/drivers/tty/serial/
Dsamsung_tty.c1 // SPDX-License-Identifier: GPL-2.0
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
12 * UERSTAT register in the UART blocks, and keeps marking some of the
21 * BJD, 04-Nov-2004
28 #include <linux/dma-mapping.h>
48 /* UART name and device definitions */
77 unsigned int fifosize; member
91 /* uart port features */
98 const unsigned int fifosize[UART_NR]; member
165 #define portaddr(port, reg) ((port)->membase + (reg))
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Dsccnxp.c1 // SPDX-License-Identifier: GPL-2.0+
24 #include <linux/platform_data/serial-sccnxp.h>
27 #define SCCNXP_NAME "uart-sccnxp"
93 #define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
94 #define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
106 unsigned int fifosize; member
112 struct uart_driver uart; member
142 .fifosize = 3,
153 .fifosize = 3,
164 .fifosize = 3,
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Dapbuart.c1 // SPDX-License-Identifier: GPL-2.0
10 * Copyright (C) 2008 Gilead Kutnick <kutnickg@zin-tech.com>
71 unsigned int max_chars = port->fifosize; in apbuart_rx_chars()
76 while (UART_RX_DATA(status) && (max_chars--)) { in apbuart_rx_chars()
81 port->icount.rx++; in apbuart_rx_chars()
89 port->icount.brk++; in apbuart_rx_chars()
93 port->icount.parity++; in apbuart_rx_chars()
95 port->icount.frame++; in apbuart_rx_chars()
98 port->icount.overrun++; in apbuart_rx_chars()
100 rsr &= port->read_status_mask; in apbuart_rx_chars()
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Dbcm63xx_uart.c1 // SPDX-License-Identifier: GPL-2.0
7 * Serial driver for BCM63xx integrated UART.
37 * - rx fifo full
38 * - rx fifo above threshold
39 * - rx fifo not empty for too long
53 * - tx fifo empty
54 * - tx fifo below threshold
71 * handy uart register accessor
76 return __raw_readl(port->membase + offset); in bcm_uart_readl()
82 __raw_writel(value, port->membase + offset); in bcm_uart_writel()
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Dmeson_uart.c1 // SPDX-License-Identifier: GPL-2.0
102 val = readl(port->membase + AML_UART_STATUS); in meson_uart_tx_empty()
111 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
113 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
120 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
122 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
130 free_irq(port->irq, port); in meson_uart_shutdown()
134 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
137 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
144 struct tty_port *tport = &port->state->port; in meson_uart_start_tx()
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Dmsm_serial.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/dma-mapping.h>
178 struct uart_port uart; member
192 return container_of(up, struct msm_port, uart); in to_msm_port()
198 writel_relaxed(val, port->membase + off); in msm_write()
204 return readl_relaxed(port->membase + off); in msm_read()
216 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxo()
228 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxoby4()
239 if (msm_port->is_uartdm) in msm_serial_set_mnd_regs()
242 if (port->uartclk == 19200000) in msm_serial_set_mnd_regs()
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Dpch_uart.c1 // SPDX-License-Identifier: GPL-2.0
37 /* Set the max number of UART port
243 * struct pch_uart_driver_data - private data structure for UART-DMA
244 * @port_type: The type of UART port
245 * @line_no: UART port line number (0, 1, 2...)
296 struct eg20t_port *priv = file->private_data; in port_show_regs()
306 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
307 "PCH EG20T port[%d] regs:\n", priv->port.line); in port_show_regs()
309 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
311 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
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Damba-pl011.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2010 ST-Ericsson SA
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
35 #include <linux/dma-mapping.h>
82 /* The size of the array - must be last */
268 unsigned int fifosize; /* vendor-specific */ member
269 unsigned int fixed_baud; /* vendor-set fixed baud rate */
291 return uap->reg_offset[reg]; in pl011_reg_to_offset()
297 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg); in pl011_read()
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Damba-pl010.c1 // SPDX-License-Identifier: GPL-2.0+
10 * This is a generic driver for ARM AMBA-type serial ports. They
11 * have a lot of 16550-like features, but are not register compatible.
65 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_tx()
67 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_tx()
76 cr = readb(uap->port.membase + UART010_CR); in pl010_start_tx()
78 writel(cr, uap->port.membase + UART010_CR); in pl010_start_tx()
87 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_rx()
89 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_rx()
97 cr = readb(uap->port.membase + UART010_CR); in pl010_disable_ms()
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D21285.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the serial port on the 21285 StrongArm-110 core logic chip.
19 #include <asm/mach-types.h>
42 static const char serial21285_name[] = "Footbridge UART";
46 * this, use bits of the private_data pointer of the uart port structure.
53 unsigned long *private_data = (unsigned long *)&port->private_data; in is_enabled()
62 unsigned long *private_data = (unsigned long *)&port->private_data; in enable()
69 unsigned long *private_data = (unsigned long *)&port->private_data; in disable()
84 * BAUD_BASE / baud - 1
88 * int(BAUD_BASE / baud - 0.5) ->
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Dliteuart.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019-2020 Antmicro <www.antmicro.com>
25 * The definitions below are true for LiteX SoC configured for 8-bit CSR Bus,
26 * 32-bit aligned.
73 struct liteuart_port *uart = to_liteuart_port(port); in liteuart_update_irq_reg() local
76 uart->irq_reg |= mask; in liteuart_update_irq_reg()
78 uart->irq_reg &= ~mask; in liteuart_update_irq_reg()
80 if (port->irq) in liteuart_update_irq_reg()
81 litex_write8(port->membase + OFF_EV_ENABLE, uart->irq_reg); in liteuart_update_irq_reg()
96 struct liteuart_port *uart = to_liteuart_port(port); in liteuart_stop_rx() local
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Dmilbeaut_usio.c1 // SPDX-License-Identifier: GPL-2.0
15 #define USIO_NAME "mlb-usio-uart"
67 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_stop_tx()
68 port->membase + MLB_USIO_REG_FCR); in mlb_usio_stop_tx()
69 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE, in mlb_usio_stop_tx()
70 port->membase + MLB_USIO_REG_SCR); in mlb_usio_stop_tx()
75 struct tty_port *tport = &port->state->port; in mlb_usio_tx_chars()
78 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_tx_chars()
79 port->membase + MLB_USIO_REG_FCR); in mlb_usio_tx_chars()
80 writeb(readb(port->membase + MLB_USIO_REG_SCR) & in mlb_usio_tx_chars()
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Dar933x_uart.c1 // SPDX-License-Identifier: GPL-2.0
3 * Atheros AR933X SoC built-in UART driver
31 #include <asm/mach-ath79/ar933x_uart.h>
35 #define DRIVER_NAME "ar933x-uart"
60 return readl(up->port.membase + offset); in ar933x_uart_read()
66 writel(value, up->port.membase + offset); in ar933x_uart_write()
98 up->ier |= AR933X_UART_INT_TX_EMPTY; in ar933x_uart_start_tx_interrupt()
99 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); in ar933x_uart_start_tx_interrupt()
104 up->ier &= ~AR933X_UART_INT_TX_EMPTY; in ar933x_uart_stop_tx_interrupt()
105 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); in ar933x_uart_stop_tx_interrupt()
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/linux-6.14.4/arch/arm64/boot/dts/exynos/google/
Dgs101.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2019-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <[email protected]>
9 #include <dt-bindings/clock/google,gs101.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/soc/samsung,exynos-usi.h>
16 #address-cells = <2>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
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/linux-6.14.4/arch/arm64/boot/dts/exynos/
Dexynosautov9.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/samsung,exynosautov9.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,boot-mode.h>
12 #include <dt-bindings/soc/samsung,exynos-usi.h>
16 #address-cells = <2>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
31 arm-pmu {
32 compatible = "arm,cortex-a76-pmu";
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Dexynos7885.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/exynos7885.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <1>;
17 interrupt-parent = <&gic>;
26 arm-a53-pmu {
27 compatible = "arm,cortex-a53-pmu";
34 interrupt-affinity = <&cpu0>,
42 arm-a73-pmu {
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Dexynos8895.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
8 #include <dt-bindings/clock/samsung,exynos8895.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <1>;
16 interrupt-parent = <&gic>;
29 arm-a53-pmu {
30 compatible = "arm,cortex-a53-pmu";
35 interrupt-affinity = <&cpu0>,
41 mongoose-m2-pmu {
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