1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for AMBA serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 * Copyright (C) 2010 ST-Ericsson SA
10 *
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
13 * Note that although they do have CTS, DCD and DSR inputs, they do
14 * not have an RI input, nor do they have DTR or RTS outputs. If
15 * required, these have to be supplied via some other means (eg, GPIO)
16 * and hooked into this driver.
17 */
18
19 #include <linux/module.h>
20 #include <linux/ioport.h>
21 #include <linux/init.h>
22 #include <linux/console.h>
23 #include <linux/platform_device.h>
24 #include <linux/sysrq.h>
25 #include <linux/device.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/serial_core.h>
29 #include <linux/serial.h>
30 #include <linux/amba/bus.h>
31 #include <linux/amba/serial.h>
32 #include <linux/clk.h>
33 #include <linux/slab.h>
34 #include <linux/dmaengine.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/scatterlist.h>
37 #include <linux/delay.h>
38 #include <linux/types.h>
39 #include <linux/of.h>
40 #include <linux/pinctrl/consumer.h>
41 #include <linux/sizes.h>
42 #include <linux/io.h>
43 #include <linux/acpi.h>
44
45 #define UART_NR 14
46
47 #define SERIAL_AMBA_MAJOR 204
48 #define SERIAL_AMBA_MINOR 64
49 #define SERIAL_AMBA_NR UART_NR
50
51 #define AMBA_ISR_PASS_LIMIT 256
52
53 #define UART_DR_ERROR (UART011_DR_OE | UART011_DR_BE | UART011_DR_PE | UART011_DR_FE)
54 #define UART_DUMMY_DR_RX BIT(16)
55
56 enum {
57 REG_DR,
58 REG_ST_DMAWM,
59 REG_ST_TIMEOUT,
60 REG_FR,
61 REG_LCRH_RX,
62 REG_LCRH_TX,
63 REG_IBRD,
64 REG_FBRD,
65 REG_CR,
66 REG_IFLS,
67 REG_IMSC,
68 REG_RIS,
69 REG_MIS,
70 REG_ICR,
71 REG_DMACR,
72 REG_ST_XFCR,
73 REG_ST_XON1,
74 REG_ST_XON2,
75 REG_ST_XOFF1,
76 REG_ST_XOFF2,
77 REG_ST_ITCR,
78 REG_ST_ITIP,
79 REG_ST_ABCR,
80 REG_ST_ABIMSC,
81
82 /* The size of the array - must be last */
83 REG_ARRAY_SIZE,
84 };
85
86 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
87 [REG_DR] = UART01x_DR,
88 [REG_FR] = UART01x_FR,
89 [REG_LCRH_RX] = UART011_LCRH,
90 [REG_LCRH_TX] = UART011_LCRH,
91 [REG_IBRD] = UART011_IBRD,
92 [REG_FBRD] = UART011_FBRD,
93 [REG_CR] = UART011_CR,
94 [REG_IFLS] = UART011_IFLS,
95 [REG_IMSC] = UART011_IMSC,
96 [REG_RIS] = UART011_RIS,
97 [REG_MIS] = UART011_MIS,
98 [REG_ICR] = UART011_ICR,
99 [REG_DMACR] = UART011_DMACR,
100 };
101
102 /* There is by now at least one vendor with differing details, so handle it */
103 struct vendor_data {
104 const u16 *reg_offset;
105 unsigned int ifls;
106 unsigned int fr_busy;
107 unsigned int fr_dsr;
108 unsigned int fr_cts;
109 unsigned int fr_ri;
110 unsigned int inv_fr;
111 bool access_32b;
112 bool oversampling;
113 bool dma_threshold;
114 bool cts_event_workaround;
115 bool always_enabled;
116 bool fixed_options;
117
118 unsigned int (*get_fifosize)(struct amba_device *dev);
119 };
120
get_fifosize_arm(struct amba_device * dev)121 static unsigned int get_fifosize_arm(struct amba_device *dev)
122 {
123 return amba_rev(dev) < 3 ? 16 : 32;
124 }
125
126 static struct vendor_data vendor_arm = {
127 .reg_offset = pl011_std_offsets,
128 .ifls = UART011_IFLS_RX4_8 | UART011_IFLS_TX4_8,
129 .fr_busy = UART01x_FR_BUSY,
130 .fr_dsr = UART01x_FR_DSR,
131 .fr_cts = UART01x_FR_CTS,
132 .fr_ri = UART011_FR_RI,
133 .oversampling = false,
134 .dma_threshold = false,
135 .cts_event_workaround = false,
136 .always_enabled = false,
137 .fixed_options = false,
138 .get_fifosize = get_fifosize_arm,
139 };
140
141 static const struct vendor_data vendor_sbsa = {
142 .reg_offset = pl011_std_offsets,
143 .fr_busy = UART01x_FR_BUSY,
144 .fr_dsr = UART01x_FR_DSR,
145 .fr_cts = UART01x_FR_CTS,
146 .fr_ri = UART011_FR_RI,
147 .access_32b = true,
148 .oversampling = false,
149 .dma_threshold = false,
150 .cts_event_workaround = false,
151 .always_enabled = true,
152 .fixed_options = true,
153 };
154
155 #ifdef CONFIG_ACPI_SPCR_TABLE
156 static const struct vendor_data vendor_qdt_qdf2400_e44 = {
157 .reg_offset = pl011_std_offsets,
158 .fr_busy = UART011_FR_TXFE,
159 .fr_dsr = UART01x_FR_DSR,
160 .fr_cts = UART01x_FR_CTS,
161 .fr_ri = UART011_FR_RI,
162 .inv_fr = UART011_FR_TXFE,
163 .access_32b = true,
164 .oversampling = false,
165 .dma_threshold = false,
166 .cts_event_workaround = false,
167 .always_enabled = true,
168 .fixed_options = true,
169 };
170 #endif
171
172 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
173 [REG_DR] = UART01x_DR,
174 [REG_ST_DMAWM] = ST_UART011_DMAWM,
175 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
176 [REG_FR] = UART01x_FR,
177 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
178 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
179 [REG_IBRD] = UART011_IBRD,
180 [REG_FBRD] = UART011_FBRD,
181 [REG_CR] = UART011_CR,
182 [REG_IFLS] = UART011_IFLS,
183 [REG_IMSC] = UART011_IMSC,
184 [REG_RIS] = UART011_RIS,
185 [REG_MIS] = UART011_MIS,
186 [REG_ICR] = UART011_ICR,
187 [REG_DMACR] = UART011_DMACR,
188 [REG_ST_XFCR] = ST_UART011_XFCR,
189 [REG_ST_XON1] = ST_UART011_XON1,
190 [REG_ST_XON2] = ST_UART011_XON2,
191 [REG_ST_XOFF1] = ST_UART011_XOFF1,
192 [REG_ST_XOFF2] = ST_UART011_XOFF2,
193 [REG_ST_ITCR] = ST_UART011_ITCR,
194 [REG_ST_ITIP] = ST_UART011_ITIP,
195 [REG_ST_ABCR] = ST_UART011_ABCR,
196 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
197 };
198
get_fifosize_st(struct amba_device * dev)199 static unsigned int get_fifosize_st(struct amba_device *dev)
200 {
201 return 64;
202 }
203
204 static struct vendor_data vendor_st = {
205 .reg_offset = pl011_st_offsets,
206 .ifls = UART011_IFLS_RX_HALF | UART011_IFLS_TX_HALF,
207 .fr_busy = UART01x_FR_BUSY,
208 .fr_dsr = UART01x_FR_DSR,
209 .fr_cts = UART01x_FR_CTS,
210 .fr_ri = UART011_FR_RI,
211 .oversampling = true,
212 .dma_threshold = true,
213 .cts_event_workaround = true,
214 .always_enabled = false,
215 .fixed_options = false,
216 .get_fifosize = get_fifosize_st,
217 };
218
219 /* Deals with DMA transactions */
220
221 struct pl011_dmabuf {
222 dma_addr_t dma;
223 size_t len;
224 char *buf;
225 };
226
227 struct pl011_dmarx_data {
228 struct dma_chan *chan;
229 struct completion complete;
230 bool use_buf_b;
231 struct pl011_dmabuf dbuf_a;
232 struct pl011_dmabuf dbuf_b;
233 dma_cookie_t cookie;
234 bool running;
235 struct timer_list timer;
236 unsigned int last_residue;
237 unsigned long last_jiffies;
238 bool auto_poll_rate;
239 unsigned int poll_rate;
240 unsigned int poll_timeout;
241 };
242
243 struct pl011_dmatx_data {
244 struct dma_chan *chan;
245 dma_addr_t dma;
246 size_t len;
247 char *buf;
248 bool queued;
249 };
250
251 enum pl011_rs485_tx_state {
252 OFF,
253 WAIT_AFTER_RTS,
254 SEND,
255 WAIT_AFTER_SEND,
256 };
257
258 /*
259 * We wrap our port structure around the generic uart_port.
260 */
261 struct uart_amba_port {
262 struct uart_port port;
263 const u16 *reg_offset;
264 struct clk *clk;
265 const struct vendor_data *vendor;
266 unsigned int im; /* interrupt mask */
267 unsigned int old_status;
268 unsigned int fifosize; /* vendor-specific */
269 unsigned int fixed_baud; /* vendor-set fixed baud rate */
270 char type[12];
271 ktime_t rs485_tx_drain_interval; /* nano */
272 enum pl011_rs485_tx_state rs485_tx_state;
273 struct hrtimer trigger_start_tx;
274 struct hrtimer trigger_stop_tx;
275 #ifdef CONFIG_DMA_ENGINE
276 /* DMA stuff */
277 unsigned int dmacr; /* dma control reg */
278 bool using_tx_dma;
279 bool using_rx_dma;
280 struct pl011_dmarx_data dmarx;
281 struct pl011_dmatx_data dmatx;
282 bool dma_probed;
283 #endif
284 };
285
286 static unsigned int pl011_tx_empty(struct uart_port *port);
287
pl011_reg_to_offset(const struct uart_amba_port * uap,unsigned int reg)288 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
289 unsigned int reg)
290 {
291 return uap->reg_offset[reg];
292 }
293
pl011_read(const struct uart_amba_port * uap,unsigned int reg)294 static unsigned int pl011_read(const struct uart_amba_port *uap,
295 unsigned int reg)
296 {
297 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
298
299 return (uap->port.iotype == UPIO_MEM32) ?
300 readl_relaxed(addr) : readw_relaxed(addr);
301 }
302
pl011_write(unsigned int val,const struct uart_amba_port * uap,unsigned int reg)303 static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
304 unsigned int reg)
305 {
306 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
307
308 if (uap->port.iotype == UPIO_MEM32)
309 writel_relaxed(val, addr);
310 else
311 writew_relaxed(val, addr);
312 }
313
314 /*
315 * Reads up to 256 characters from the FIFO or until it's empty and
316 * inserts them into the TTY layer. Returns the number of characters
317 * read from the FIFO.
318 */
pl011_fifo_to_tty(struct uart_amba_port * uap)319 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
320 {
321 unsigned int ch, fifotaken;
322 int sysrq;
323 u16 status;
324 u8 flag;
325
326 for (fifotaken = 0; fifotaken != 256; fifotaken++) {
327 status = pl011_read(uap, REG_FR);
328 if (status & UART01x_FR_RXFE)
329 break;
330
331 /* Take chars from the FIFO and update status */
332 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
333 flag = TTY_NORMAL;
334 uap->port.icount.rx++;
335
336 if (unlikely(ch & UART_DR_ERROR)) {
337 if (ch & UART011_DR_BE) {
338 ch &= ~(UART011_DR_FE | UART011_DR_PE);
339 uap->port.icount.brk++;
340 if (uart_handle_break(&uap->port))
341 continue;
342 } else if (ch & UART011_DR_PE) {
343 uap->port.icount.parity++;
344 } else if (ch & UART011_DR_FE) {
345 uap->port.icount.frame++;
346 }
347 if (ch & UART011_DR_OE)
348 uap->port.icount.overrun++;
349
350 ch &= uap->port.read_status_mask;
351
352 if (ch & UART011_DR_BE)
353 flag = TTY_BREAK;
354 else if (ch & UART011_DR_PE)
355 flag = TTY_PARITY;
356 else if (ch & UART011_DR_FE)
357 flag = TTY_FRAME;
358 }
359
360 sysrq = uart_prepare_sysrq_char(&uap->port, ch & 255);
361 if (!sysrq)
362 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
363 }
364
365 return fifotaken;
366 }
367
368 /*
369 * All the DMA operation mode stuff goes inside this ifdef.
370 * This assumes that you have a generic DMA device interface,
371 * no custom DMA interfaces are supported.
372 */
373 #ifdef CONFIG_DMA_ENGINE
374
375 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
376
pl011_dmabuf_init(struct dma_chan * chan,struct pl011_dmabuf * db,enum dma_data_direction dir)377 static int pl011_dmabuf_init(struct dma_chan *chan, struct pl011_dmabuf *db,
378 enum dma_data_direction dir)
379 {
380 db->buf = dma_alloc_coherent(chan->device->dev, PL011_DMA_BUFFER_SIZE,
381 &db->dma, GFP_KERNEL);
382 if (!db->buf)
383 return -ENOMEM;
384 db->len = PL011_DMA_BUFFER_SIZE;
385
386 return 0;
387 }
388
pl011_dmabuf_free(struct dma_chan * chan,struct pl011_dmabuf * db,enum dma_data_direction dir)389 static void pl011_dmabuf_free(struct dma_chan *chan, struct pl011_dmabuf *db,
390 enum dma_data_direction dir)
391 {
392 if (db->buf) {
393 dma_free_coherent(chan->device->dev,
394 PL011_DMA_BUFFER_SIZE, db->buf, db->dma);
395 }
396 }
397
pl011_dma_probe(struct uart_amba_port * uap)398 static void pl011_dma_probe(struct uart_amba_port *uap)
399 {
400 /* DMA is the sole user of the platform data right now */
401 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
402 struct device *dev = uap->port.dev;
403 struct dma_slave_config tx_conf = {
404 .dst_addr = uap->port.mapbase +
405 pl011_reg_to_offset(uap, REG_DR),
406 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
407 .direction = DMA_MEM_TO_DEV,
408 .dst_maxburst = uap->fifosize >> 1,
409 .device_fc = false,
410 };
411 struct dma_chan *chan;
412 dma_cap_mask_t mask;
413
414 uap->dma_probed = true;
415 chan = dma_request_chan(dev, "tx");
416 if (IS_ERR(chan)) {
417 if (PTR_ERR(chan) == -EPROBE_DEFER) {
418 uap->dma_probed = false;
419 return;
420 }
421
422 /* We need platform data */
423 if (!plat || !plat->dma_filter) {
424 dev_dbg(uap->port.dev, "no DMA platform data\n");
425 return;
426 }
427
428 /* Try to acquire a generic DMA engine slave TX channel */
429 dma_cap_zero(mask);
430 dma_cap_set(DMA_SLAVE, mask);
431
432 chan = dma_request_channel(mask, plat->dma_filter,
433 plat->dma_tx_param);
434 if (!chan) {
435 dev_err(uap->port.dev, "no TX DMA channel!\n");
436 return;
437 }
438 }
439
440 dmaengine_slave_config(chan, &tx_conf);
441 uap->dmatx.chan = chan;
442
443 dev_info(uap->port.dev, "DMA channel TX %s\n",
444 dma_chan_name(uap->dmatx.chan));
445
446 /* Optionally make use of an RX channel as well */
447 chan = dma_request_chan(dev, "rx");
448
449 if (IS_ERR(chan) && plat && plat->dma_rx_param) {
450 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
451
452 if (!chan) {
453 dev_err(uap->port.dev, "no RX DMA channel!\n");
454 return;
455 }
456 }
457
458 if (!IS_ERR(chan)) {
459 struct dma_slave_config rx_conf = {
460 .src_addr = uap->port.mapbase +
461 pl011_reg_to_offset(uap, REG_DR),
462 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
463 .direction = DMA_DEV_TO_MEM,
464 .src_maxburst = uap->fifosize >> 2,
465 .device_fc = false,
466 };
467 struct dma_slave_caps caps;
468
469 /*
470 * Some DMA controllers provide information on their capabilities.
471 * If the controller does, check for suitable residue processing
472 * otherwise assime all is well.
473 */
474 if (dma_get_slave_caps(chan, &caps) == 0) {
475 if (caps.residue_granularity ==
476 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
477 dma_release_channel(chan);
478 dev_info(uap->port.dev,
479 "RX DMA disabled - no residue processing\n");
480 return;
481 }
482 }
483 dmaengine_slave_config(chan, &rx_conf);
484 uap->dmarx.chan = chan;
485
486 uap->dmarx.auto_poll_rate = false;
487 if (plat && plat->dma_rx_poll_enable) {
488 /* Set poll rate if specified. */
489 if (plat->dma_rx_poll_rate) {
490 uap->dmarx.auto_poll_rate = false;
491 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
492 } else {
493 /*
494 * 100 ms defaults to poll rate if not
495 * specified. This will be adjusted with
496 * the baud rate at set_termios.
497 */
498 uap->dmarx.auto_poll_rate = true;
499 uap->dmarx.poll_rate = 100;
500 }
501 /* 3 secs defaults poll_timeout if not specified. */
502 if (plat->dma_rx_poll_timeout)
503 uap->dmarx.poll_timeout =
504 plat->dma_rx_poll_timeout;
505 else
506 uap->dmarx.poll_timeout = 3000;
507 } else if (!plat && dev->of_node) {
508 uap->dmarx.auto_poll_rate =
509 of_property_read_bool(dev->of_node, "auto-poll");
510 if (uap->dmarx.auto_poll_rate) {
511 u32 x;
512
513 if (of_property_read_u32(dev->of_node, "poll-rate-ms", &x) == 0)
514 uap->dmarx.poll_rate = x;
515 else
516 uap->dmarx.poll_rate = 100;
517 if (of_property_read_u32(dev->of_node, "poll-timeout-ms", &x) == 0)
518 uap->dmarx.poll_timeout = x;
519 else
520 uap->dmarx.poll_timeout = 3000;
521 }
522 }
523 dev_info(uap->port.dev, "DMA channel RX %s\n",
524 dma_chan_name(uap->dmarx.chan));
525 }
526 }
527
pl011_dma_remove(struct uart_amba_port * uap)528 static void pl011_dma_remove(struct uart_amba_port *uap)
529 {
530 if (uap->dmatx.chan)
531 dma_release_channel(uap->dmatx.chan);
532 if (uap->dmarx.chan)
533 dma_release_channel(uap->dmarx.chan);
534 }
535
536 /* Forward declare these for the refill routine */
537 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
538 static void pl011_start_tx_pio(struct uart_amba_port *uap);
539
540 /*
541 * The current DMA TX buffer has been sent.
542 * Try to queue up another DMA buffer.
543 */
pl011_dma_tx_callback(void * data)544 static void pl011_dma_tx_callback(void *data)
545 {
546 struct uart_amba_port *uap = data;
547 struct tty_port *tport = &uap->port.state->port;
548 struct pl011_dmatx_data *dmatx = &uap->dmatx;
549 unsigned long flags;
550 u16 dmacr;
551
552 uart_port_lock_irqsave(&uap->port, &flags);
553 if (uap->dmatx.queued)
554 dma_unmap_single(dmatx->chan->device->dev, dmatx->dma,
555 dmatx->len, DMA_TO_DEVICE);
556
557 dmacr = uap->dmacr;
558 uap->dmacr = dmacr & ~UART011_TXDMAE;
559 pl011_write(uap->dmacr, uap, REG_DMACR);
560
561 /*
562 * If TX DMA was disabled, it means that we've stopped the DMA for
563 * some reason (eg, XOFF received, or we want to send an X-char.)
564 *
565 * Note: we need to be careful here of a potential race between DMA
566 * and the rest of the driver - if the driver disables TX DMA while
567 * a TX buffer completing, we must update the tx queued status to
568 * get further refills (hence we check dmacr).
569 */
570 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
571 kfifo_is_empty(&tport->xmit_fifo)) {
572 uap->dmatx.queued = false;
573 uart_port_unlock_irqrestore(&uap->port, flags);
574 return;
575 }
576
577 if (pl011_dma_tx_refill(uap) <= 0)
578 /*
579 * We didn't queue a DMA buffer for some reason, but we
580 * have data pending to be sent. Re-enable the TX IRQ.
581 */
582 pl011_start_tx_pio(uap);
583
584 uart_port_unlock_irqrestore(&uap->port, flags);
585 }
586
587 /*
588 * Try to refill the TX DMA buffer.
589 * Locking: called with port lock held and IRQs disabled.
590 * Returns:
591 * 1 if we queued up a TX DMA buffer.
592 * 0 if we didn't want to handle this by DMA
593 * <0 on error
594 */
pl011_dma_tx_refill(struct uart_amba_port * uap)595 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
596 {
597 struct pl011_dmatx_data *dmatx = &uap->dmatx;
598 struct dma_chan *chan = dmatx->chan;
599 struct dma_device *dma_dev = chan->device;
600 struct dma_async_tx_descriptor *desc;
601 struct tty_port *tport = &uap->port.state->port;
602 unsigned int count;
603
604 /*
605 * Try to avoid the overhead involved in using DMA if the
606 * transaction fits in the first half of the FIFO, by using
607 * the standard interrupt handling. This ensures that we
608 * issue a uart_write_wakeup() at the appropriate time.
609 */
610 count = kfifo_len(&tport->xmit_fifo);
611 if (count < (uap->fifosize >> 1)) {
612 uap->dmatx.queued = false;
613 return 0;
614 }
615
616 /*
617 * Bodge: don't send the last character by DMA, as this
618 * will prevent XON from notifying us to restart DMA.
619 */
620 count -= 1;
621
622 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
623 if (count > PL011_DMA_BUFFER_SIZE)
624 count = PL011_DMA_BUFFER_SIZE;
625
626 count = kfifo_out_peek(&tport->xmit_fifo, dmatx->buf, count);
627 dmatx->len = count;
628 dmatx->dma = dma_map_single(dma_dev->dev, dmatx->buf, count,
629 DMA_TO_DEVICE);
630 if (dmatx->dma == DMA_MAPPING_ERROR) {
631 uap->dmatx.queued = false;
632 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
633 return -EBUSY;
634 }
635
636 desc = dmaengine_prep_slave_single(chan, dmatx->dma, dmatx->len, DMA_MEM_TO_DEV,
637 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
638 if (!desc) {
639 dma_unmap_single(dma_dev->dev, dmatx->dma, dmatx->len, DMA_TO_DEVICE);
640 uap->dmatx.queued = false;
641 /*
642 * If DMA cannot be used right now, we complete this
643 * transaction via IRQ and let the TTY layer retry.
644 */
645 dev_dbg(uap->port.dev, "TX DMA busy\n");
646 return -EBUSY;
647 }
648
649 /* Some data to go along to the callback */
650 desc->callback = pl011_dma_tx_callback;
651 desc->callback_param = uap;
652
653 /* All errors should happen at prepare time */
654 dmaengine_submit(desc);
655
656 /* Fire the DMA transaction */
657 dma_dev->device_issue_pending(chan);
658
659 uap->dmacr |= UART011_TXDMAE;
660 pl011_write(uap->dmacr, uap, REG_DMACR);
661 uap->dmatx.queued = true;
662
663 /*
664 * Now we know that DMA will fire, so advance the ring buffer
665 * with the stuff we just dispatched.
666 */
667 uart_xmit_advance(&uap->port, count);
668
669 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
670 uart_write_wakeup(&uap->port);
671
672 return 1;
673 }
674
675 /*
676 * We received a transmit interrupt without a pending X-char but with
677 * pending characters.
678 * Locking: called with port lock held and IRQs disabled.
679 * Returns:
680 * false if we want to use PIO to transmit
681 * true if we queued a DMA buffer
682 */
pl011_dma_tx_irq(struct uart_amba_port * uap)683 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
684 {
685 if (!uap->using_tx_dma)
686 return false;
687
688 /*
689 * If we already have a TX buffer queued, but received a
690 * TX interrupt, it will be because we've just sent an X-char.
691 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
692 */
693 if (uap->dmatx.queued) {
694 uap->dmacr |= UART011_TXDMAE;
695 pl011_write(uap->dmacr, uap, REG_DMACR);
696 uap->im &= ~UART011_TXIM;
697 pl011_write(uap->im, uap, REG_IMSC);
698 return true;
699 }
700
701 /*
702 * We don't have a TX buffer queued, so try to queue one.
703 * If we successfully queued a buffer, mask the TX IRQ.
704 */
705 if (pl011_dma_tx_refill(uap) > 0) {
706 uap->im &= ~UART011_TXIM;
707 pl011_write(uap->im, uap, REG_IMSC);
708 return true;
709 }
710 return false;
711 }
712
713 /*
714 * Stop the DMA transmit (eg, due to received XOFF).
715 * Locking: called with port lock held and IRQs disabled.
716 */
pl011_dma_tx_stop(struct uart_amba_port * uap)717 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
718 {
719 if (uap->dmatx.queued) {
720 uap->dmacr &= ~UART011_TXDMAE;
721 pl011_write(uap->dmacr, uap, REG_DMACR);
722 }
723 }
724
725 /*
726 * Try to start a DMA transmit, or in the case of an XON/OFF
727 * character queued for send, try to get that character out ASAP.
728 * Locking: called with port lock held and IRQs disabled.
729 * Returns:
730 * false if we want the TX IRQ to be enabled
731 * true if we have a buffer queued
732 */
pl011_dma_tx_start(struct uart_amba_port * uap)733 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
734 {
735 u16 dmacr;
736
737 if (!uap->using_tx_dma)
738 return false;
739
740 if (!uap->port.x_char) {
741 /* no X-char, try to push chars out in DMA mode */
742 bool ret = true;
743
744 if (!uap->dmatx.queued) {
745 if (pl011_dma_tx_refill(uap) > 0) {
746 uap->im &= ~UART011_TXIM;
747 pl011_write(uap->im, uap, REG_IMSC);
748 } else {
749 ret = false;
750 }
751 } else if (!(uap->dmacr & UART011_TXDMAE)) {
752 uap->dmacr |= UART011_TXDMAE;
753 pl011_write(uap->dmacr, uap, REG_DMACR);
754 }
755 return ret;
756 }
757
758 /*
759 * We have an X-char to send. Disable DMA to prevent it loading
760 * the TX fifo, and then see if we can stuff it into the FIFO.
761 */
762 dmacr = uap->dmacr;
763 uap->dmacr &= ~UART011_TXDMAE;
764 pl011_write(uap->dmacr, uap, REG_DMACR);
765
766 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
767 /*
768 * No space in the FIFO, so enable the transmit interrupt
769 * so we know when there is space. Note that once we've
770 * loaded the character, we should just re-enable DMA.
771 */
772 return false;
773 }
774
775 pl011_write(uap->port.x_char, uap, REG_DR);
776 uap->port.icount.tx++;
777 uap->port.x_char = 0;
778
779 /* Success - restore the DMA state */
780 uap->dmacr = dmacr;
781 pl011_write(dmacr, uap, REG_DMACR);
782
783 return true;
784 }
785
786 /*
787 * Flush the transmit buffer.
788 * Locking: called with port lock held and IRQs disabled.
789 */
pl011_dma_flush_buffer(struct uart_port * port)790 static void pl011_dma_flush_buffer(struct uart_port *port)
791 __releases(&uap->port.lock)
792 __acquires(&uap->port.lock)
793 {
794 struct uart_amba_port *uap =
795 container_of(port, struct uart_amba_port, port);
796
797 if (!uap->using_tx_dma)
798 return;
799
800 dmaengine_terminate_async(uap->dmatx.chan);
801
802 if (uap->dmatx.queued) {
803 dma_unmap_single(uap->dmatx.chan->device->dev, uap->dmatx.dma,
804 uap->dmatx.len, DMA_TO_DEVICE);
805 uap->dmatx.queued = false;
806 uap->dmacr &= ~UART011_TXDMAE;
807 pl011_write(uap->dmacr, uap, REG_DMACR);
808 }
809 }
810
811 static void pl011_dma_rx_callback(void *data);
812
pl011_dma_rx_trigger_dma(struct uart_amba_port * uap)813 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
814 {
815 struct dma_chan *rxchan = uap->dmarx.chan;
816 struct pl011_dmarx_data *dmarx = &uap->dmarx;
817 struct dma_async_tx_descriptor *desc;
818 struct pl011_dmabuf *dbuf;
819
820 if (!rxchan)
821 return -EIO;
822
823 /* Start the RX DMA job */
824 dbuf = uap->dmarx.use_buf_b ?
825 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
826 desc = dmaengine_prep_slave_single(rxchan, dbuf->dma, dbuf->len,
827 DMA_DEV_TO_MEM,
828 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
829 /*
830 * If the DMA engine is busy and cannot prepare a
831 * channel, no big deal, the driver will fall back
832 * to interrupt mode as a result of this error code.
833 */
834 if (!desc) {
835 uap->dmarx.running = false;
836 dmaengine_terminate_all(rxchan);
837 return -EBUSY;
838 }
839
840 /* Some data to go along to the callback */
841 desc->callback = pl011_dma_rx_callback;
842 desc->callback_param = uap;
843 dmarx->cookie = dmaengine_submit(desc);
844 dma_async_issue_pending(rxchan);
845
846 uap->dmacr |= UART011_RXDMAE;
847 pl011_write(uap->dmacr, uap, REG_DMACR);
848 uap->dmarx.running = true;
849
850 uap->im &= ~UART011_RXIM;
851 pl011_write(uap->im, uap, REG_IMSC);
852
853 return 0;
854 }
855
856 /*
857 * This is called when either the DMA job is complete, or
858 * the FIFO timeout interrupt occurred. This must be called
859 * with the port spinlock uap->port.lock held.
860 */
pl011_dma_rx_chars(struct uart_amba_port * uap,u32 pending,bool use_buf_b,bool readfifo)861 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
862 u32 pending, bool use_buf_b,
863 bool readfifo)
864 {
865 struct tty_port *port = &uap->port.state->port;
866 struct pl011_dmabuf *dbuf = use_buf_b ?
867 &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
868 int dma_count = 0;
869 u32 fifotaken = 0; /* only used for vdbg() */
870
871 struct pl011_dmarx_data *dmarx = &uap->dmarx;
872 int dmataken = 0;
873
874 if (uap->dmarx.poll_rate) {
875 /* The data can be taken by polling */
876 dmataken = dbuf->len - dmarx->last_residue;
877 /* Recalculate the pending size */
878 if (pending >= dmataken)
879 pending -= dmataken;
880 }
881
882 /* Pick the remain data from the DMA */
883 if (pending) {
884 /*
885 * First take all chars in the DMA pipe, then look in the FIFO.
886 * Note that tty_insert_flip_buf() tries to take as many chars
887 * as it can.
888 */
889 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken, pending);
890
891 uap->port.icount.rx += dma_count;
892 if (dma_count < pending)
893 dev_warn(uap->port.dev,
894 "couldn't insert all characters (TTY is full?)\n");
895 }
896
897 /* Reset the last_residue for Rx DMA poll */
898 if (uap->dmarx.poll_rate)
899 dmarx->last_residue = dbuf->len;
900
901 /*
902 * Only continue with trying to read the FIFO if all DMA chars have
903 * been taken first.
904 */
905 if (dma_count == pending && readfifo) {
906 /* Clear any error flags */
907 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
908 UART011_FEIS, uap, REG_ICR);
909
910 /*
911 * If we read all the DMA'd characters, and we had an
912 * incomplete buffer, that could be due to an rx error, or
913 * maybe we just timed out. Read any pending chars and check
914 * the error status.
915 *
916 * Error conditions will only occur in the FIFO, these will
917 * trigger an immediate interrupt and stop the DMA job, so we
918 * will always find the error in the FIFO, never in the DMA
919 * buffer.
920 */
921 fifotaken = pl011_fifo_to_tty(uap);
922 }
923
924 dev_vdbg(uap->port.dev,
925 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
926 dma_count, fifotaken);
927 tty_flip_buffer_push(port);
928 }
929
pl011_dma_rx_irq(struct uart_amba_port * uap)930 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
931 {
932 struct pl011_dmarx_data *dmarx = &uap->dmarx;
933 struct dma_chan *rxchan = dmarx->chan;
934 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ?
935 &dmarx->dbuf_b : &dmarx->dbuf_a;
936 size_t pending;
937 struct dma_tx_state state;
938 enum dma_status dmastat;
939
940 /*
941 * Pause the transfer so we can trust the current counter,
942 * do this before we pause the PL011 block, else we may
943 * overflow the FIFO.
944 */
945 if (dmaengine_pause(rxchan))
946 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
947 dmastat = rxchan->device->device_tx_status(rxchan,
948 dmarx->cookie, &state);
949 if (dmastat != DMA_PAUSED)
950 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
951
952 /* Disable RX DMA - incoming data will wait in the FIFO */
953 uap->dmacr &= ~UART011_RXDMAE;
954 pl011_write(uap->dmacr, uap, REG_DMACR);
955 uap->dmarx.running = false;
956
957 pending = dbuf->len - state.residue;
958 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
959 /* Then we terminate the transfer - we now know our residue */
960 dmaengine_terminate_all(rxchan);
961
962 /*
963 * This will take the chars we have so far and insert
964 * into the framework.
965 */
966 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
967
968 /* Switch buffer & re-trigger DMA job */
969 dmarx->use_buf_b = !dmarx->use_buf_b;
970 if (pl011_dma_rx_trigger_dma(uap)) {
971 dev_dbg(uap->port.dev,
972 "could not retrigger RX DMA job fall back to interrupt mode\n");
973 uap->im |= UART011_RXIM;
974 pl011_write(uap->im, uap, REG_IMSC);
975 }
976 }
977
pl011_dma_rx_callback(void * data)978 static void pl011_dma_rx_callback(void *data)
979 {
980 struct uart_amba_port *uap = data;
981 struct pl011_dmarx_data *dmarx = &uap->dmarx;
982 struct dma_chan *rxchan = dmarx->chan;
983 bool lastbuf = dmarx->use_buf_b;
984 struct pl011_dmabuf *dbuf = dmarx->use_buf_b ?
985 &dmarx->dbuf_b : &dmarx->dbuf_a;
986 size_t pending;
987 struct dma_tx_state state;
988 int ret;
989
990 /*
991 * This completion interrupt occurs typically when the
992 * RX buffer is totally stuffed but no timeout has yet
993 * occurred. When that happens, we just want the RX
994 * routine to flush out the secondary DMA buffer while
995 * we immediately trigger the next DMA job.
996 */
997 uart_port_lock_irq(&uap->port);
998 /*
999 * Rx data can be taken by the UART interrupts during
1000 * the DMA irq handler. So we check the residue here.
1001 */
1002 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1003 pending = dbuf->len - state.residue;
1004 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1005 /* Then we terminate the transfer - we now know our residue */
1006 dmaengine_terminate_all(rxchan);
1007
1008 uap->dmarx.running = false;
1009 dmarx->use_buf_b = !lastbuf;
1010 ret = pl011_dma_rx_trigger_dma(uap);
1011
1012 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1013 uart_unlock_and_check_sysrq(&uap->port);
1014 /*
1015 * Do this check after we picked the DMA chars so we don't
1016 * get some IRQ immediately from RX.
1017 */
1018 if (ret) {
1019 dev_dbg(uap->port.dev,
1020 "could not retrigger RX DMA job fall back to interrupt mode\n");
1021 uap->im |= UART011_RXIM;
1022 pl011_write(uap->im, uap, REG_IMSC);
1023 }
1024 }
1025
1026 /*
1027 * Stop accepting received characters, when we're shutting down or
1028 * suspending this port.
1029 * Locking: called with port lock held and IRQs disabled.
1030 */
pl011_dma_rx_stop(struct uart_amba_port * uap)1031 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1032 {
1033 if (!uap->using_rx_dma)
1034 return;
1035
1036 /* FIXME. Just disable the DMA enable */
1037 uap->dmacr &= ~UART011_RXDMAE;
1038 pl011_write(uap->dmacr, uap, REG_DMACR);
1039 }
1040
1041 /*
1042 * Timer handler for Rx DMA polling.
1043 * Every polling, It checks the residue in the dma buffer and transfer
1044 * data to the tty. Also, last_residue is updated for the next polling.
1045 */
pl011_dma_rx_poll(struct timer_list * t)1046 static void pl011_dma_rx_poll(struct timer_list *t)
1047 {
1048 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
1049 struct tty_port *port = &uap->port.state->port;
1050 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1051 struct dma_chan *rxchan = uap->dmarx.chan;
1052 unsigned long flags;
1053 unsigned int dmataken = 0;
1054 unsigned int size = 0;
1055 struct pl011_dmabuf *dbuf;
1056 int dma_count;
1057 struct dma_tx_state state;
1058
1059 dbuf = dmarx->use_buf_b ? &uap->dmarx.dbuf_b : &uap->dmarx.dbuf_a;
1060 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1061 if (likely(state.residue < dmarx->last_residue)) {
1062 dmataken = dbuf->len - dmarx->last_residue;
1063 size = dmarx->last_residue - state.residue;
1064 dma_count = tty_insert_flip_string(port, dbuf->buf + dmataken,
1065 size);
1066 if (dma_count == size)
1067 dmarx->last_residue = state.residue;
1068 dmarx->last_jiffies = jiffies;
1069 }
1070 tty_flip_buffer_push(port);
1071
1072 /*
1073 * If no data is received in poll_timeout, the driver will fall back
1074 * to interrupt mode. We will retrigger DMA at the first interrupt.
1075 */
1076 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1077 > uap->dmarx.poll_timeout) {
1078 uart_port_lock_irqsave(&uap->port, &flags);
1079 pl011_dma_rx_stop(uap);
1080 uap->im |= UART011_RXIM;
1081 pl011_write(uap->im, uap, REG_IMSC);
1082 uart_port_unlock_irqrestore(&uap->port, flags);
1083
1084 uap->dmarx.running = false;
1085 dmaengine_terminate_all(rxchan);
1086 del_timer(&uap->dmarx.timer);
1087 } else {
1088 mod_timer(&uap->dmarx.timer,
1089 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1090 }
1091 }
1092
pl011_dma_startup(struct uart_amba_port * uap)1093 static void pl011_dma_startup(struct uart_amba_port *uap)
1094 {
1095 int ret;
1096
1097 if (!uap->dma_probed)
1098 pl011_dma_probe(uap);
1099
1100 if (!uap->dmatx.chan)
1101 return;
1102
1103 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1104 if (!uap->dmatx.buf) {
1105 uap->port.fifosize = uap->fifosize;
1106 return;
1107 }
1108
1109 uap->dmatx.len = PL011_DMA_BUFFER_SIZE;
1110
1111 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1112 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1113 uap->using_tx_dma = true;
1114
1115 if (!uap->dmarx.chan)
1116 goto skip_rx;
1117
1118 /* Allocate and map DMA RX buffers */
1119 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_a,
1120 DMA_FROM_DEVICE);
1121 if (ret) {
1122 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1123 "RX buffer A", ret);
1124 goto skip_rx;
1125 }
1126
1127 ret = pl011_dmabuf_init(uap->dmarx.chan, &uap->dmarx.dbuf_b,
1128 DMA_FROM_DEVICE);
1129 if (ret) {
1130 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1131 "RX buffer B", ret);
1132 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a,
1133 DMA_FROM_DEVICE);
1134 goto skip_rx;
1135 }
1136
1137 uap->using_rx_dma = true;
1138
1139 skip_rx:
1140 /* Turn on DMA error (RX/TX will be enabled on demand) */
1141 uap->dmacr |= UART011_DMAONERR;
1142 pl011_write(uap->dmacr, uap, REG_DMACR);
1143
1144 /*
1145 * ST Micro variants has some specific dma burst threshold
1146 * compensation. Set this to 16 bytes, so burst will only
1147 * be issued above/below 16 bytes.
1148 */
1149 if (uap->vendor->dma_threshold)
1150 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1151 uap, REG_ST_DMAWM);
1152
1153 if (uap->using_rx_dma) {
1154 if (pl011_dma_rx_trigger_dma(uap))
1155 dev_dbg(uap->port.dev,
1156 "could not trigger initial RX DMA job, fall back to interrupt mode\n");
1157 if (uap->dmarx.poll_rate) {
1158 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
1159 mod_timer(&uap->dmarx.timer,
1160 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1161 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1162 uap->dmarx.last_jiffies = jiffies;
1163 }
1164 }
1165 }
1166
pl011_dma_shutdown(struct uart_amba_port * uap)1167 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1168 {
1169 if (!(uap->using_tx_dma || uap->using_rx_dma))
1170 return;
1171
1172 /* Disable RX and TX DMA */
1173 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1174 cpu_relax();
1175
1176 uart_port_lock_irq(&uap->port);
1177 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1178 pl011_write(uap->dmacr, uap, REG_DMACR);
1179 uart_port_unlock_irq(&uap->port);
1180
1181 if (uap->using_tx_dma) {
1182 /* In theory, this should already be done by pl011_dma_flush_buffer */
1183 dmaengine_terminate_all(uap->dmatx.chan);
1184 if (uap->dmatx.queued) {
1185 dma_unmap_single(uap->dmatx.chan->device->dev,
1186 uap->dmatx.dma, uap->dmatx.len,
1187 DMA_TO_DEVICE);
1188 uap->dmatx.queued = false;
1189 }
1190
1191 kfree(uap->dmatx.buf);
1192 uap->using_tx_dma = false;
1193 }
1194
1195 if (uap->using_rx_dma) {
1196 dmaengine_terminate_all(uap->dmarx.chan);
1197 /* Clean up the RX DMA */
1198 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_a, DMA_FROM_DEVICE);
1199 pl011_dmabuf_free(uap->dmarx.chan, &uap->dmarx.dbuf_b, DMA_FROM_DEVICE);
1200 if (uap->dmarx.poll_rate)
1201 del_timer_sync(&uap->dmarx.timer);
1202 uap->using_rx_dma = false;
1203 }
1204 }
1205
pl011_dma_rx_available(struct uart_amba_port * uap)1206 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1207 {
1208 return uap->using_rx_dma;
1209 }
1210
pl011_dma_rx_running(struct uart_amba_port * uap)1211 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1212 {
1213 return uap->using_rx_dma && uap->dmarx.running;
1214 }
1215
1216 #else
1217 /* Blank functions if the DMA engine is not available */
pl011_dma_remove(struct uart_amba_port * uap)1218 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1219 {
1220 }
1221
pl011_dma_startup(struct uart_amba_port * uap)1222 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1223 {
1224 }
1225
pl011_dma_shutdown(struct uart_amba_port * uap)1226 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1227 {
1228 }
1229
pl011_dma_tx_irq(struct uart_amba_port * uap)1230 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1231 {
1232 return false;
1233 }
1234
pl011_dma_tx_stop(struct uart_amba_port * uap)1235 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1236 {
1237 }
1238
pl011_dma_tx_start(struct uart_amba_port * uap)1239 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1240 {
1241 return false;
1242 }
1243
pl011_dma_rx_irq(struct uart_amba_port * uap)1244 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1245 {
1246 }
1247
pl011_dma_rx_stop(struct uart_amba_port * uap)1248 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1249 {
1250 }
1251
pl011_dma_rx_trigger_dma(struct uart_amba_port * uap)1252 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1253 {
1254 return -EIO;
1255 }
1256
pl011_dma_rx_available(struct uart_amba_port * uap)1257 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1258 {
1259 return false;
1260 }
1261
pl011_dma_rx_running(struct uart_amba_port * uap)1262 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1263 {
1264 return false;
1265 }
1266
1267 #define pl011_dma_flush_buffer NULL
1268 #endif
1269
pl011_rs485_tx_stop(struct uart_amba_port * uap)1270 static void pl011_rs485_tx_stop(struct uart_amba_port *uap)
1271 {
1272 struct uart_port *port = &uap->port;
1273 u32 cr;
1274
1275 if (uap->rs485_tx_state == SEND)
1276 uap->rs485_tx_state = WAIT_AFTER_SEND;
1277
1278 if (uap->rs485_tx_state == WAIT_AFTER_SEND) {
1279 /* Schedule hrtimer if tx queue not empty */
1280 if (!pl011_tx_empty(port)) {
1281 hrtimer_start(&uap->trigger_stop_tx,
1282 uap->rs485_tx_drain_interval,
1283 HRTIMER_MODE_REL);
1284 return;
1285 }
1286 if (port->rs485.delay_rts_after_send > 0) {
1287 hrtimer_start(&uap->trigger_stop_tx,
1288 ms_to_ktime(port->rs485.delay_rts_after_send),
1289 HRTIMER_MODE_REL);
1290 return;
1291 }
1292 /* Continue without any delay */
1293 } else if (uap->rs485_tx_state == WAIT_AFTER_RTS) {
1294 hrtimer_try_to_cancel(&uap->trigger_start_tx);
1295 }
1296
1297 cr = pl011_read(uap, REG_CR);
1298
1299 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1300 cr &= ~UART011_CR_RTS;
1301 else
1302 cr |= UART011_CR_RTS;
1303
1304 /* Disable the transmitter and reenable the transceiver */
1305 cr &= ~UART011_CR_TXE;
1306 cr |= UART011_CR_RXE;
1307 pl011_write(cr, uap, REG_CR);
1308
1309 uap->rs485_tx_state = OFF;
1310 }
1311
pl011_stop_tx(struct uart_port * port)1312 static void pl011_stop_tx(struct uart_port *port)
1313 {
1314 struct uart_amba_port *uap =
1315 container_of(port, struct uart_amba_port, port);
1316
1317 if (port->rs485.flags & SER_RS485_ENABLED &&
1318 uap->rs485_tx_state == WAIT_AFTER_RTS) {
1319 pl011_rs485_tx_stop(uap);
1320 return;
1321 }
1322
1323 uap->im &= ~UART011_TXIM;
1324 pl011_write(uap->im, uap, REG_IMSC);
1325 pl011_dma_tx_stop(uap);
1326
1327 if (port->rs485.flags & SER_RS485_ENABLED &&
1328 uap->rs485_tx_state != OFF)
1329 pl011_rs485_tx_stop(uap);
1330 }
1331
1332 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1333
1334 /* Start TX with programmed I/O only (no DMA) */
pl011_start_tx_pio(struct uart_amba_port * uap)1335 static void pl011_start_tx_pio(struct uart_amba_port *uap)
1336 {
1337 if (pl011_tx_chars(uap, false)) {
1338 uap->im |= UART011_TXIM;
1339 pl011_write(uap->im, uap, REG_IMSC);
1340 }
1341 }
1342
pl011_rs485_tx_start(struct uart_amba_port * uap)1343 static void pl011_rs485_tx_start(struct uart_amba_port *uap)
1344 {
1345 struct uart_port *port = &uap->port;
1346 u32 cr;
1347
1348 if (uap->rs485_tx_state == WAIT_AFTER_RTS) {
1349 uap->rs485_tx_state = SEND;
1350 return;
1351 }
1352 if (uap->rs485_tx_state == WAIT_AFTER_SEND) {
1353 hrtimer_try_to_cancel(&uap->trigger_stop_tx);
1354 uap->rs485_tx_state = SEND;
1355 return;
1356 }
1357 /* uap->rs485_tx_state == OFF */
1358 /* Enable transmitter */
1359 cr = pl011_read(uap, REG_CR);
1360 cr |= UART011_CR_TXE;
1361 /* Disable receiver if half-duplex */
1362 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
1363 cr &= ~UART011_CR_RXE;
1364
1365 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
1366 cr &= ~UART011_CR_RTS;
1367 else
1368 cr |= UART011_CR_RTS;
1369
1370 pl011_write(cr, uap, REG_CR);
1371
1372 if (port->rs485.delay_rts_before_send > 0) {
1373 uap->rs485_tx_state = WAIT_AFTER_RTS;
1374 hrtimer_start(&uap->trigger_start_tx,
1375 ms_to_ktime(port->rs485.delay_rts_before_send),
1376 HRTIMER_MODE_REL);
1377 } else {
1378 uap->rs485_tx_state = SEND;
1379 }
1380 }
1381
pl011_start_tx(struct uart_port * port)1382 static void pl011_start_tx(struct uart_port *port)
1383 {
1384 struct uart_amba_port *uap =
1385 container_of(port, struct uart_amba_port, port);
1386
1387 if ((uap->port.rs485.flags & SER_RS485_ENABLED) &&
1388 uap->rs485_tx_state != SEND) {
1389 pl011_rs485_tx_start(uap);
1390 if (uap->rs485_tx_state == WAIT_AFTER_RTS)
1391 return;
1392 }
1393
1394 if (!pl011_dma_tx_start(uap))
1395 pl011_start_tx_pio(uap);
1396 }
1397
pl011_trigger_start_tx(struct hrtimer * t)1398 static enum hrtimer_restart pl011_trigger_start_tx(struct hrtimer *t)
1399 {
1400 struct uart_amba_port *uap =
1401 container_of(t, struct uart_amba_port, trigger_start_tx);
1402 unsigned long flags;
1403
1404 uart_port_lock_irqsave(&uap->port, &flags);
1405 if (uap->rs485_tx_state == WAIT_AFTER_RTS)
1406 pl011_start_tx(&uap->port);
1407 uart_port_unlock_irqrestore(&uap->port, flags);
1408
1409 return HRTIMER_NORESTART;
1410 }
1411
pl011_trigger_stop_tx(struct hrtimer * t)1412 static enum hrtimer_restart pl011_trigger_stop_tx(struct hrtimer *t)
1413 {
1414 struct uart_amba_port *uap =
1415 container_of(t, struct uart_amba_port, trigger_stop_tx);
1416 unsigned long flags;
1417
1418 uart_port_lock_irqsave(&uap->port, &flags);
1419 if (uap->rs485_tx_state == WAIT_AFTER_SEND)
1420 pl011_rs485_tx_stop(uap);
1421 uart_port_unlock_irqrestore(&uap->port, flags);
1422
1423 return HRTIMER_NORESTART;
1424 }
1425
pl011_stop_rx(struct uart_port * port)1426 static void pl011_stop_rx(struct uart_port *port)
1427 {
1428 struct uart_amba_port *uap =
1429 container_of(port, struct uart_amba_port, port);
1430
1431 uap->im &= ~(UART011_RXIM | UART011_RTIM | UART011_FEIM |
1432 UART011_PEIM | UART011_BEIM | UART011_OEIM);
1433 pl011_write(uap->im, uap, REG_IMSC);
1434
1435 pl011_dma_rx_stop(uap);
1436 }
1437
pl011_throttle_rx(struct uart_port * port)1438 static void pl011_throttle_rx(struct uart_port *port)
1439 {
1440 unsigned long flags;
1441
1442 uart_port_lock_irqsave(port, &flags);
1443 pl011_stop_rx(port);
1444 uart_port_unlock_irqrestore(port, flags);
1445 }
1446
pl011_enable_ms(struct uart_port * port)1447 static void pl011_enable_ms(struct uart_port *port)
1448 {
1449 struct uart_amba_port *uap =
1450 container_of(port, struct uart_amba_port, port);
1451
1452 uap->im |= UART011_RIMIM | UART011_CTSMIM | UART011_DCDMIM | UART011_DSRMIM;
1453 pl011_write(uap->im, uap, REG_IMSC);
1454 }
1455
pl011_rx_chars(struct uart_amba_port * uap)1456 static void pl011_rx_chars(struct uart_amba_port *uap)
1457 __releases(&uap->port.lock)
1458 __acquires(&uap->port.lock)
1459 {
1460 pl011_fifo_to_tty(uap);
1461
1462 uart_port_unlock(&uap->port);
1463 tty_flip_buffer_push(&uap->port.state->port);
1464 /*
1465 * If we were temporarily out of DMA mode for a while,
1466 * attempt to switch back to DMA mode again.
1467 */
1468 if (pl011_dma_rx_available(uap)) {
1469 if (pl011_dma_rx_trigger_dma(uap)) {
1470 dev_dbg(uap->port.dev,
1471 "could not trigger RX DMA job fall back to interrupt mode again\n");
1472 uap->im |= UART011_RXIM;
1473 pl011_write(uap->im, uap, REG_IMSC);
1474 } else {
1475 #ifdef CONFIG_DMA_ENGINE
1476 /* Start Rx DMA poll */
1477 if (uap->dmarx.poll_rate) {
1478 uap->dmarx.last_jiffies = jiffies;
1479 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1480 mod_timer(&uap->dmarx.timer,
1481 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1482 }
1483 #endif
1484 }
1485 }
1486 uart_port_lock(&uap->port);
1487 }
1488
pl011_tx_char(struct uart_amba_port * uap,unsigned char c,bool from_irq)1489 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1490 bool from_irq)
1491 {
1492 if (unlikely(!from_irq) &&
1493 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1494 return false; /* unable to transmit character */
1495
1496 pl011_write(c, uap, REG_DR);
1497 uap->port.icount.tx++;
1498
1499 return true;
1500 }
1501
1502 /* Returns true if tx interrupts have to be (kept) enabled */
pl011_tx_chars(struct uart_amba_port * uap,bool from_irq)1503 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1504 {
1505 struct tty_port *tport = &uap->port.state->port;
1506 int count = uap->fifosize >> 1;
1507
1508 if (uap->port.x_char) {
1509 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1510 return true;
1511 uap->port.x_char = 0;
1512 --count;
1513 }
1514 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(&uap->port)) {
1515 pl011_stop_tx(&uap->port);
1516 return false;
1517 }
1518
1519 /* If we are using DMA mode, try to send some characters. */
1520 if (pl011_dma_tx_irq(uap))
1521 return true;
1522
1523 while (1) {
1524 unsigned char c;
1525
1526 if (likely(from_irq) && count-- == 0)
1527 break;
1528
1529 if (!kfifo_peek(&tport->xmit_fifo, &c))
1530 break;
1531
1532 if (!pl011_tx_char(uap, c, from_irq))
1533 break;
1534
1535 kfifo_skip(&tport->xmit_fifo);
1536 }
1537
1538 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
1539 uart_write_wakeup(&uap->port);
1540
1541 if (kfifo_is_empty(&tport->xmit_fifo)) {
1542 pl011_stop_tx(&uap->port);
1543 return false;
1544 }
1545 return true;
1546 }
1547
pl011_modem_status(struct uart_amba_port * uap)1548 static void pl011_modem_status(struct uart_amba_port *uap)
1549 {
1550 unsigned int status, delta;
1551
1552 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1553
1554 delta = status ^ uap->old_status;
1555 uap->old_status = status;
1556
1557 if (!delta)
1558 return;
1559
1560 if (delta & UART01x_FR_DCD)
1561 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1562
1563 if (delta & uap->vendor->fr_dsr)
1564 uap->port.icount.dsr++;
1565
1566 if (delta & uap->vendor->fr_cts)
1567 uart_handle_cts_change(&uap->port,
1568 status & uap->vendor->fr_cts);
1569
1570 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1571 }
1572
check_apply_cts_event_workaround(struct uart_amba_port * uap)1573 static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1574 {
1575 if (!uap->vendor->cts_event_workaround)
1576 return;
1577
1578 /* workaround to make sure that all bits are unlocked.. */
1579 pl011_write(0x00, uap, REG_ICR);
1580
1581 /*
1582 * WA: introduce 26ns(1 uart clk) delay before W1C;
1583 * single apb access will incur 2 pclk(133.12Mhz) delay,
1584 * so add 2 dummy reads
1585 */
1586 pl011_read(uap, REG_ICR);
1587 pl011_read(uap, REG_ICR);
1588 }
1589
pl011_int(int irq,void * dev_id)1590 static irqreturn_t pl011_int(int irq, void *dev_id)
1591 {
1592 struct uart_amba_port *uap = dev_id;
1593 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1594 int handled = 0;
1595
1596 uart_port_lock(&uap->port);
1597 status = pl011_read(uap, REG_RIS) & uap->im;
1598 if (status) {
1599 do {
1600 check_apply_cts_event_workaround(uap);
1601
1602 pl011_write(status & ~(UART011_TXIS | UART011_RTIS | UART011_RXIS),
1603 uap, REG_ICR);
1604
1605 if (status & (UART011_RTIS | UART011_RXIS)) {
1606 if (pl011_dma_rx_running(uap))
1607 pl011_dma_rx_irq(uap);
1608 else
1609 pl011_rx_chars(uap);
1610 }
1611 if (status & (UART011_DSRMIS | UART011_DCDMIS |
1612 UART011_CTSMIS | UART011_RIMIS))
1613 pl011_modem_status(uap);
1614 if (status & UART011_TXIS)
1615 pl011_tx_chars(uap, true);
1616
1617 if (pass_counter-- == 0)
1618 break;
1619
1620 status = pl011_read(uap, REG_RIS) & uap->im;
1621 } while (status != 0);
1622 handled = 1;
1623 }
1624
1625 uart_unlock_and_check_sysrq(&uap->port);
1626
1627 return IRQ_RETVAL(handled);
1628 }
1629
pl011_tx_empty(struct uart_port * port)1630 static unsigned int pl011_tx_empty(struct uart_port *port)
1631 {
1632 struct uart_amba_port *uap =
1633 container_of(port, struct uart_amba_port, port);
1634
1635 /* Allow feature register bits to be inverted to work around errata */
1636 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1637
1638 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1639 0 : TIOCSER_TEMT;
1640 }
1641
pl011_maybe_set_bit(bool cond,unsigned int * ptr,unsigned int mask)1642 static void pl011_maybe_set_bit(bool cond, unsigned int *ptr, unsigned int mask)
1643 {
1644 if (cond)
1645 *ptr |= mask;
1646 }
1647
pl011_get_mctrl(struct uart_port * port)1648 static unsigned int pl011_get_mctrl(struct uart_port *port)
1649 {
1650 struct uart_amba_port *uap =
1651 container_of(port, struct uart_amba_port, port);
1652 unsigned int result = 0;
1653 unsigned int status = pl011_read(uap, REG_FR);
1654
1655 pl011_maybe_set_bit(status & UART01x_FR_DCD, &result, TIOCM_CAR);
1656 pl011_maybe_set_bit(status & uap->vendor->fr_dsr, &result, TIOCM_DSR);
1657 pl011_maybe_set_bit(status & uap->vendor->fr_cts, &result, TIOCM_CTS);
1658 pl011_maybe_set_bit(status & uap->vendor->fr_ri, &result, TIOCM_RNG);
1659
1660 return result;
1661 }
1662
pl011_assign_bit(bool cond,unsigned int * ptr,unsigned int mask)1663 static void pl011_assign_bit(bool cond, unsigned int *ptr, unsigned int mask)
1664 {
1665 if (cond)
1666 *ptr |= mask;
1667 else
1668 *ptr &= ~mask;
1669 }
1670
pl011_set_mctrl(struct uart_port * port,unsigned int mctrl)1671 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1672 {
1673 struct uart_amba_port *uap =
1674 container_of(port, struct uart_amba_port, port);
1675 unsigned int cr;
1676
1677 cr = pl011_read(uap, REG_CR);
1678
1679 pl011_assign_bit(mctrl & TIOCM_RTS, &cr, UART011_CR_RTS);
1680 pl011_assign_bit(mctrl & TIOCM_DTR, &cr, UART011_CR_DTR);
1681 pl011_assign_bit(mctrl & TIOCM_OUT1, &cr, UART011_CR_OUT1);
1682 pl011_assign_bit(mctrl & TIOCM_OUT2, &cr, UART011_CR_OUT2);
1683 pl011_assign_bit(mctrl & TIOCM_LOOP, &cr, UART011_CR_LBE);
1684
1685 if (port->status & UPSTAT_AUTORTS) {
1686 /* We need to disable auto-RTS if we want to turn RTS off */
1687 pl011_assign_bit(mctrl & TIOCM_RTS, &cr, UART011_CR_RTSEN);
1688 }
1689
1690 pl011_write(cr, uap, REG_CR);
1691 }
1692
pl011_break_ctl(struct uart_port * port,int break_state)1693 static void pl011_break_ctl(struct uart_port *port, int break_state)
1694 {
1695 struct uart_amba_port *uap =
1696 container_of(port, struct uart_amba_port, port);
1697 unsigned long flags;
1698 unsigned int lcr_h;
1699
1700 uart_port_lock_irqsave(&uap->port, &flags);
1701 lcr_h = pl011_read(uap, REG_LCRH_TX);
1702 if (break_state == -1)
1703 lcr_h |= UART01x_LCRH_BRK;
1704 else
1705 lcr_h &= ~UART01x_LCRH_BRK;
1706 pl011_write(lcr_h, uap, REG_LCRH_TX);
1707 uart_port_unlock_irqrestore(&uap->port, flags);
1708 }
1709
1710 #ifdef CONFIG_CONSOLE_POLL
1711
pl011_quiesce_irqs(struct uart_port * port)1712 static void pl011_quiesce_irqs(struct uart_port *port)
1713 {
1714 struct uart_amba_port *uap =
1715 container_of(port, struct uart_amba_port, port);
1716
1717 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1718 /*
1719 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1720 * we simply mask it. start_tx() will unmask it.
1721 *
1722 * Note we can race with start_tx(), and if the race happens, the
1723 * polling user might get another interrupt just after we clear it.
1724 * But it should be OK and can happen even w/o the race, e.g.
1725 * controller immediately got some new data and raised the IRQ.
1726 *
1727 * And whoever uses polling routines assumes that it manages the device
1728 * (including tx queue), so we're also fine with start_tx()'s caller
1729 * side.
1730 */
1731 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1732 REG_IMSC);
1733 }
1734
pl011_get_poll_char(struct uart_port * port)1735 static int pl011_get_poll_char(struct uart_port *port)
1736 {
1737 struct uart_amba_port *uap =
1738 container_of(port, struct uart_amba_port, port);
1739 unsigned int status;
1740
1741 /*
1742 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1743 * debugger.
1744 */
1745 pl011_quiesce_irqs(port);
1746
1747 status = pl011_read(uap, REG_FR);
1748 if (status & UART01x_FR_RXFE)
1749 return NO_POLL_CHAR;
1750
1751 return pl011_read(uap, REG_DR);
1752 }
1753
pl011_put_poll_char(struct uart_port * port,unsigned char ch)1754 static void pl011_put_poll_char(struct uart_port *port, unsigned char ch)
1755 {
1756 struct uart_amba_port *uap =
1757 container_of(port, struct uart_amba_port, port);
1758
1759 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1760 cpu_relax();
1761
1762 pl011_write(ch, uap, REG_DR);
1763 }
1764
1765 #endif /* CONFIG_CONSOLE_POLL */
1766
pl011_hwinit(struct uart_port * port)1767 static int pl011_hwinit(struct uart_port *port)
1768 {
1769 struct uart_amba_port *uap =
1770 container_of(port, struct uart_amba_port, port);
1771 int retval;
1772
1773 /* Optionaly enable pins to be muxed in and configured */
1774 pinctrl_pm_select_default_state(port->dev);
1775
1776 /*
1777 * Try to enable the clock producer.
1778 */
1779 retval = clk_prepare_enable(uap->clk);
1780 if (retval)
1781 return retval;
1782
1783 uap->port.uartclk = clk_get_rate(uap->clk);
1784
1785 /* Clear pending error and receive interrupts */
1786 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1787 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1788 uap, REG_ICR);
1789
1790 /*
1791 * Save interrupts enable mask, and enable RX interrupts in case if
1792 * the interrupt is used for NMI entry.
1793 */
1794 uap->im = pl011_read(uap, REG_IMSC);
1795 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1796
1797 if (dev_get_platdata(uap->port.dev)) {
1798 struct amba_pl011_data *plat;
1799
1800 plat = dev_get_platdata(uap->port.dev);
1801 if (plat->init)
1802 plat->init();
1803 }
1804 return 0;
1805 }
1806
pl011_split_lcrh(const struct uart_amba_port * uap)1807 static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1808 {
1809 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1810 pl011_reg_to_offset(uap, REG_LCRH_TX);
1811 }
1812
pl011_write_lcr_h(struct uart_amba_port * uap,unsigned int lcr_h)1813 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1814 {
1815 pl011_write(lcr_h, uap, REG_LCRH_RX);
1816 if (pl011_split_lcrh(uap)) {
1817 int i;
1818 /*
1819 * Wait 10 PCLKs before writing LCRH_TX register,
1820 * to get this delay write read only register 10 times
1821 */
1822 for (i = 0; i < 10; ++i)
1823 pl011_write(0xff, uap, REG_MIS);
1824 pl011_write(lcr_h, uap, REG_LCRH_TX);
1825 }
1826 }
1827
pl011_allocate_irq(struct uart_amba_port * uap)1828 static int pl011_allocate_irq(struct uart_amba_port *uap)
1829 {
1830 pl011_write(uap->im, uap, REG_IMSC);
1831
1832 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap);
1833 }
1834
1835 /*
1836 * Enable interrupts, only timeouts when using DMA
1837 * if initial RX DMA job failed, start in interrupt mode
1838 * as well.
1839 */
pl011_enable_interrupts(struct uart_amba_port * uap)1840 static void pl011_enable_interrupts(struct uart_amba_port *uap)
1841 {
1842 unsigned long flags;
1843 unsigned int i;
1844
1845 uart_port_lock_irqsave(&uap->port, &flags);
1846
1847 /* Clear out any spuriously appearing RX interrupts */
1848 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1849
1850 /*
1851 * RXIS is asserted only when the RX FIFO transitions from below
1852 * to above the trigger threshold. If the RX FIFO is already
1853 * full to the threshold this can't happen and RXIS will now be
1854 * stuck off. Drain the RX FIFO explicitly to fix this:
1855 */
1856 for (i = 0; i < uap->fifosize * 2; ++i) {
1857 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1858 break;
1859
1860 pl011_read(uap, REG_DR);
1861 }
1862
1863 uap->im = UART011_RTIM;
1864 if (!pl011_dma_rx_running(uap))
1865 uap->im |= UART011_RXIM;
1866 pl011_write(uap->im, uap, REG_IMSC);
1867 uart_port_unlock_irqrestore(&uap->port, flags);
1868 }
1869
pl011_unthrottle_rx(struct uart_port * port)1870 static void pl011_unthrottle_rx(struct uart_port *port)
1871 {
1872 struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port);
1873 unsigned long flags;
1874
1875 uart_port_lock_irqsave(&uap->port, &flags);
1876
1877 uap->im = UART011_RTIM;
1878 if (!pl011_dma_rx_running(uap))
1879 uap->im |= UART011_RXIM;
1880
1881 pl011_write(uap->im, uap, REG_IMSC);
1882
1883 #ifdef CONFIG_DMA_ENGINE
1884 if (uap->using_rx_dma) {
1885 uap->dmacr |= UART011_RXDMAE;
1886 pl011_write(uap->dmacr, uap, REG_DMACR);
1887 }
1888 #endif
1889
1890 uart_port_unlock_irqrestore(&uap->port, flags);
1891 }
1892
pl011_startup(struct uart_port * port)1893 static int pl011_startup(struct uart_port *port)
1894 {
1895 struct uart_amba_port *uap =
1896 container_of(port, struct uart_amba_port, port);
1897 unsigned int cr;
1898 int retval;
1899
1900 retval = pl011_hwinit(port);
1901 if (retval)
1902 goto clk_dis;
1903
1904 retval = pl011_allocate_irq(uap);
1905 if (retval)
1906 goto clk_dis;
1907
1908 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1909
1910 uart_port_lock_irq(&uap->port);
1911
1912 cr = pl011_read(uap, REG_CR);
1913 cr &= UART011_CR_RTS | UART011_CR_DTR;
1914 cr |= UART01x_CR_UARTEN | UART011_CR_RXE;
1915
1916 if (!(port->rs485.flags & SER_RS485_ENABLED))
1917 cr |= UART011_CR_TXE;
1918
1919 pl011_write(cr, uap, REG_CR);
1920
1921 uart_port_unlock_irq(&uap->port);
1922
1923 /*
1924 * initialise the old status of the modem signals
1925 */
1926 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1927
1928 /* Startup DMA */
1929 pl011_dma_startup(uap);
1930
1931 pl011_enable_interrupts(uap);
1932
1933 return 0;
1934
1935 clk_dis:
1936 clk_disable_unprepare(uap->clk);
1937 return retval;
1938 }
1939
sbsa_uart_startup(struct uart_port * port)1940 static int sbsa_uart_startup(struct uart_port *port)
1941 {
1942 struct uart_amba_port *uap =
1943 container_of(port, struct uart_amba_port, port);
1944 int retval;
1945
1946 retval = pl011_hwinit(port);
1947 if (retval)
1948 return retval;
1949
1950 retval = pl011_allocate_irq(uap);
1951 if (retval)
1952 return retval;
1953
1954 /* The SBSA UART does not support any modem status lines. */
1955 uap->old_status = 0;
1956
1957 pl011_enable_interrupts(uap);
1958
1959 return 0;
1960 }
1961
pl011_shutdown_channel(struct uart_amba_port * uap,unsigned int lcrh)1962 static void pl011_shutdown_channel(struct uart_amba_port *uap, unsigned int lcrh)
1963 {
1964 unsigned long val;
1965
1966 val = pl011_read(uap, lcrh);
1967 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1968 pl011_write(val, uap, lcrh);
1969 }
1970
1971 /*
1972 * disable the port. It should not disable RTS and DTR.
1973 * Also RTS and DTR state should be preserved to restore
1974 * it during startup().
1975 */
pl011_disable_uart(struct uart_amba_port * uap)1976 static void pl011_disable_uart(struct uart_amba_port *uap)
1977 {
1978 unsigned int cr;
1979
1980 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1981 uart_port_lock_irq(&uap->port);
1982 cr = pl011_read(uap, REG_CR);
1983 cr &= UART011_CR_RTS | UART011_CR_DTR;
1984 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1985 pl011_write(cr, uap, REG_CR);
1986 uart_port_unlock_irq(&uap->port);
1987
1988 /*
1989 * disable break condition and fifos
1990 */
1991 pl011_shutdown_channel(uap, REG_LCRH_RX);
1992 if (pl011_split_lcrh(uap))
1993 pl011_shutdown_channel(uap, REG_LCRH_TX);
1994 }
1995
pl011_disable_interrupts(struct uart_amba_port * uap)1996 static void pl011_disable_interrupts(struct uart_amba_port *uap)
1997 {
1998 uart_port_lock_irq(&uap->port);
1999
2000 /* mask all interrupts and clear all pending ones */
2001 uap->im = 0;
2002 pl011_write(uap->im, uap, REG_IMSC);
2003 pl011_write(0xffff, uap, REG_ICR);
2004
2005 uart_port_unlock_irq(&uap->port);
2006 }
2007
pl011_shutdown(struct uart_port * port)2008 static void pl011_shutdown(struct uart_port *port)
2009 {
2010 struct uart_amba_port *uap =
2011 container_of(port, struct uart_amba_port, port);
2012
2013 pl011_disable_interrupts(uap);
2014
2015 pl011_dma_shutdown(uap);
2016
2017 if ((port->rs485.flags & SER_RS485_ENABLED && uap->rs485_tx_state != OFF))
2018 pl011_rs485_tx_stop(uap);
2019
2020 free_irq(uap->port.irq, uap);
2021
2022 pl011_disable_uart(uap);
2023
2024 /*
2025 * Shut down the clock producer
2026 */
2027 clk_disable_unprepare(uap->clk);
2028 /* Optionally let pins go into sleep states */
2029 pinctrl_pm_select_sleep_state(port->dev);
2030
2031 if (dev_get_platdata(uap->port.dev)) {
2032 struct amba_pl011_data *plat;
2033
2034 plat = dev_get_platdata(uap->port.dev);
2035 if (plat->exit)
2036 plat->exit();
2037 }
2038
2039 if (uap->port.ops->flush_buffer)
2040 uap->port.ops->flush_buffer(port);
2041 }
2042
sbsa_uart_shutdown(struct uart_port * port)2043 static void sbsa_uart_shutdown(struct uart_port *port)
2044 {
2045 struct uart_amba_port *uap =
2046 container_of(port, struct uart_amba_port, port);
2047
2048 pl011_disable_interrupts(uap);
2049
2050 free_irq(uap->port.irq, uap);
2051
2052 if (uap->port.ops->flush_buffer)
2053 uap->port.ops->flush_buffer(port);
2054 }
2055
2056 static void
pl011_setup_status_masks(struct uart_port * port,struct ktermios * termios)2057 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
2058 {
2059 port->read_status_mask = UART011_DR_OE | 255;
2060 if (termios->c_iflag & INPCK)
2061 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
2062 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2063 port->read_status_mask |= UART011_DR_BE;
2064
2065 /*
2066 * Characters to ignore
2067 */
2068 port->ignore_status_mask = 0;
2069 if (termios->c_iflag & IGNPAR)
2070 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
2071 if (termios->c_iflag & IGNBRK) {
2072 port->ignore_status_mask |= UART011_DR_BE;
2073 /*
2074 * If we're ignoring parity and break indicators,
2075 * ignore overruns too (for real raw support).
2076 */
2077 if (termios->c_iflag & IGNPAR)
2078 port->ignore_status_mask |= UART011_DR_OE;
2079 }
2080
2081 /*
2082 * Ignore all characters if CREAD is not set.
2083 */
2084 if ((termios->c_cflag & CREAD) == 0)
2085 port->ignore_status_mask |= UART_DUMMY_DR_RX;
2086 }
2087
2088 static void
pl011_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)2089 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
2090 const struct ktermios *old)
2091 {
2092 struct uart_amba_port *uap =
2093 container_of(port, struct uart_amba_port, port);
2094 unsigned int lcr_h, old_cr;
2095 unsigned long flags;
2096 unsigned int baud, quot, clkdiv;
2097 unsigned int bits;
2098
2099 if (uap->vendor->oversampling)
2100 clkdiv = 8;
2101 else
2102 clkdiv = 16;
2103
2104 /*
2105 * Ask the core to calculate the divisor for us.
2106 */
2107 baud = uart_get_baud_rate(port, termios, old, 0,
2108 port->uartclk / clkdiv);
2109 #ifdef CONFIG_DMA_ENGINE
2110 /*
2111 * Adjust RX DMA polling rate with baud rate if not specified.
2112 */
2113 if (uap->dmarx.auto_poll_rate)
2114 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
2115 #endif
2116
2117 if (baud > port->uartclk / 16)
2118 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
2119 else
2120 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
2121
2122 switch (termios->c_cflag & CSIZE) {
2123 case CS5:
2124 lcr_h = UART01x_LCRH_WLEN_5;
2125 break;
2126 case CS6:
2127 lcr_h = UART01x_LCRH_WLEN_6;
2128 break;
2129 case CS7:
2130 lcr_h = UART01x_LCRH_WLEN_7;
2131 break;
2132 default: // CS8
2133 lcr_h = UART01x_LCRH_WLEN_8;
2134 break;
2135 }
2136 if (termios->c_cflag & CSTOPB)
2137 lcr_h |= UART01x_LCRH_STP2;
2138 if (termios->c_cflag & PARENB) {
2139 lcr_h |= UART01x_LCRH_PEN;
2140 if (!(termios->c_cflag & PARODD))
2141 lcr_h |= UART01x_LCRH_EPS;
2142 if (termios->c_cflag & CMSPAR)
2143 lcr_h |= UART011_LCRH_SPS;
2144 }
2145 if (uap->fifosize > 1)
2146 lcr_h |= UART01x_LCRH_FEN;
2147
2148 bits = tty_get_frame_size(termios->c_cflag);
2149
2150 uart_port_lock_irqsave(port, &flags);
2151
2152 /*
2153 * Update the per-port timeout.
2154 */
2155 uart_update_timeout(port, termios->c_cflag, baud);
2156
2157 /*
2158 * Calculate the approximated time it takes to transmit one character
2159 * with the given baud rate. We use this as the poll interval when we
2160 * wait for the tx queue to empty.
2161 */
2162 uap->rs485_tx_drain_interval = ns_to_ktime(DIV_ROUND_UP(bits * NSEC_PER_SEC, baud));
2163
2164 pl011_setup_status_masks(port, termios);
2165
2166 if (UART_ENABLE_MS(port, termios->c_cflag))
2167 pl011_enable_ms(port);
2168
2169 if (port->rs485.flags & SER_RS485_ENABLED)
2170 termios->c_cflag &= ~CRTSCTS;
2171
2172 old_cr = pl011_read(uap, REG_CR);
2173
2174 if (termios->c_cflag & CRTSCTS) {
2175 if (old_cr & UART011_CR_RTS)
2176 old_cr |= UART011_CR_RTSEN;
2177
2178 old_cr |= UART011_CR_CTSEN;
2179 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
2180 } else {
2181 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2182 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
2183 }
2184
2185 if (uap->vendor->oversampling) {
2186 if (baud > port->uartclk / 16)
2187 old_cr |= ST_UART011_CR_OVSFACT;
2188 else
2189 old_cr &= ~ST_UART011_CR_OVSFACT;
2190 }
2191
2192 /*
2193 * Workaround for the ST Micro oversampling variants to
2194 * increase the bitrate slightly, by lowering the divisor,
2195 * to avoid delayed sampling of start bit at high speeds,
2196 * else we see data corruption.
2197 */
2198 if (uap->vendor->oversampling) {
2199 if (baud >= 3000000 && baud < 3250000 && quot > 1)
2200 quot -= 1;
2201 else if (baud > 3250000 && quot > 2)
2202 quot -= 2;
2203 }
2204 /* Set baud rate */
2205 pl011_write(quot & 0x3f, uap, REG_FBRD);
2206 pl011_write(quot >> 6, uap, REG_IBRD);
2207
2208 /*
2209 * ----------v----------v----------v----------v-----
2210 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
2211 * REG_FBRD & REG_IBRD.
2212 * ----------^----------^----------^----------^-----
2213 */
2214 pl011_write_lcr_h(uap, lcr_h);
2215
2216 /*
2217 * Receive was disabled by pl011_disable_uart during shutdown.
2218 * Need to reenable receive if you need to use a tty_driver
2219 * returns from tty_find_polling_driver() after a port shutdown.
2220 */
2221 old_cr |= UART011_CR_RXE;
2222 pl011_write(old_cr, uap, REG_CR);
2223
2224 uart_port_unlock_irqrestore(port, flags);
2225 }
2226
2227 static void
sbsa_uart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)2228 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2229 const struct ktermios *old)
2230 {
2231 struct uart_amba_port *uap =
2232 container_of(port, struct uart_amba_port, port);
2233 unsigned long flags;
2234
2235 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2236
2237 /* The SBSA UART only supports 8n1 without hardware flow control. */
2238 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2239 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2240 termios->c_cflag |= CS8 | CLOCAL;
2241
2242 uart_port_lock_irqsave(port, &flags);
2243 uart_update_timeout(port, CS8, uap->fixed_baud);
2244 pl011_setup_status_masks(port, termios);
2245 uart_port_unlock_irqrestore(port, flags);
2246 }
2247
pl011_type(struct uart_port * port)2248 static const char *pl011_type(struct uart_port *port)
2249 {
2250 struct uart_amba_port *uap =
2251 container_of(port, struct uart_amba_port, port);
2252 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2253 }
2254
2255 /*
2256 * Configure/autoconfigure the port.
2257 */
pl011_config_port(struct uart_port * port,int flags)2258 static void pl011_config_port(struct uart_port *port, int flags)
2259 {
2260 if (flags & UART_CONFIG_TYPE)
2261 port->type = PORT_AMBA;
2262 }
2263
2264 /*
2265 * verify the new serial_struct (for TIOCSSERIAL).
2266 */
pl011_verify_port(struct uart_port * port,struct serial_struct * ser)2267 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2268 {
2269 int ret = 0;
2270
2271 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2272 ret = -EINVAL;
2273 if (ser->irq < 0 || ser->irq >= irq_get_nr_irqs())
2274 ret = -EINVAL;
2275 if (ser->baud_base < 9600)
2276 ret = -EINVAL;
2277 if (port->mapbase != (unsigned long)ser->iomem_base)
2278 ret = -EINVAL;
2279 return ret;
2280 }
2281
pl011_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)2282 static int pl011_rs485_config(struct uart_port *port, struct ktermios *termios,
2283 struct serial_rs485 *rs485)
2284 {
2285 struct uart_amba_port *uap =
2286 container_of(port, struct uart_amba_port, port);
2287
2288 if (port->rs485.flags & SER_RS485_ENABLED)
2289 pl011_rs485_tx_stop(uap);
2290
2291 /* Make sure auto RTS is disabled */
2292 if (rs485->flags & SER_RS485_ENABLED) {
2293 u32 cr = pl011_read(uap, REG_CR);
2294
2295 cr &= ~UART011_CR_RTSEN;
2296 pl011_write(cr, uap, REG_CR);
2297 port->status &= ~UPSTAT_AUTORTS;
2298 }
2299
2300 return 0;
2301 }
2302
2303 static const struct uart_ops amba_pl011_pops = {
2304 .tx_empty = pl011_tx_empty,
2305 .set_mctrl = pl011_set_mctrl,
2306 .get_mctrl = pl011_get_mctrl,
2307 .stop_tx = pl011_stop_tx,
2308 .start_tx = pl011_start_tx,
2309 .stop_rx = pl011_stop_rx,
2310 .throttle = pl011_throttle_rx,
2311 .unthrottle = pl011_unthrottle_rx,
2312 .enable_ms = pl011_enable_ms,
2313 .break_ctl = pl011_break_ctl,
2314 .startup = pl011_startup,
2315 .shutdown = pl011_shutdown,
2316 .flush_buffer = pl011_dma_flush_buffer,
2317 .set_termios = pl011_set_termios,
2318 .type = pl011_type,
2319 .config_port = pl011_config_port,
2320 .verify_port = pl011_verify_port,
2321 #ifdef CONFIG_CONSOLE_POLL
2322 .poll_init = pl011_hwinit,
2323 .poll_get_char = pl011_get_poll_char,
2324 .poll_put_char = pl011_put_poll_char,
2325 #endif
2326 };
2327
sbsa_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)2328 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2329 {
2330 }
2331
sbsa_uart_get_mctrl(struct uart_port * port)2332 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2333 {
2334 return 0;
2335 }
2336
2337 static const struct uart_ops sbsa_uart_pops = {
2338 .tx_empty = pl011_tx_empty,
2339 .set_mctrl = sbsa_uart_set_mctrl,
2340 .get_mctrl = sbsa_uart_get_mctrl,
2341 .stop_tx = pl011_stop_tx,
2342 .start_tx = pl011_start_tx,
2343 .stop_rx = pl011_stop_rx,
2344 .startup = sbsa_uart_startup,
2345 .shutdown = sbsa_uart_shutdown,
2346 .set_termios = sbsa_uart_set_termios,
2347 .type = pl011_type,
2348 .config_port = pl011_config_port,
2349 .verify_port = pl011_verify_port,
2350 #ifdef CONFIG_CONSOLE_POLL
2351 .poll_init = pl011_hwinit,
2352 .poll_get_char = pl011_get_poll_char,
2353 .poll_put_char = pl011_put_poll_char,
2354 #endif
2355 };
2356
2357 static struct uart_amba_port *amba_ports[UART_NR];
2358
2359 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2360
pl011_console_putchar(struct uart_port * port,unsigned char ch)2361 static void pl011_console_putchar(struct uart_port *port, unsigned char ch)
2362 {
2363 struct uart_amba_port *uap =
2364 container_of(port, struct uart_amba_port, port);
2365
2366 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2367 cpu_relax();
2368 pl011_write(ch, uap, REG_DR);
2369 }
2370
2371 static void
pl011_console_write(struct console * co,const char * s,unsigned int count)2372 pl011_console_write(struct console *co, const char *s, unsigned int count)
2373 {
2374 struct uart_amba_port *uap = amba_ports[co->index];
2375 unsigned int old_cr = 0, new_cr;
2376 unsigned long flags;
2377 int locked = 1;
2378
2379 clk_enable(uap->clk);
2380
2381 if (oops_in_progress)
2382 locked = uart_port_trylock_irqsave(&uap->port, &flags);
2383 else
2384 uart_port_lock_irqsave(&uap->port, &flags);
2385
2386 /*
2387 * First save the CR then disable the interrupts
2388 */
2389 if (!uap->vendor->always_enabled) {
2390 old_cr = pl011_read(uap, REG_CR);
2391 new_cr = old_cr & ~UART011_CR_CTSEN;
2392 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2393 pl011_write(new_cr, uap, REG_CR);
2394 }
2395
2396 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2397
2398 /*
2399 * Finally, wait for transmitter to become empty and restore the
2400 * TCR. Allow feature register bits to be inverted to work around
2401 * errata.
2402 */
2403 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2404 & uap->vendor->fr_busy)
2405 cpu_relax();
2406 if (!uap->vendor->always_enabled)
2407 pl011_write(old_cr, uap, REG_CR);
2408
2409 if (locked)
2410 uart_port_unlock_irqrestore(&uap->port, flags);
2411
2412 clk_disable(uap->clk);
2413 }
2414
pl011_console_get_options(struct uart_amba_port * uap,int * baud,int * parity,int * bits)2415 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2416 int *parity, int *bits)
2417 {
2418 unsigned int lcr_h, ibrd, fbrd;
2419
2420 if (!(pl011_read(uap, REG_CR) & UART01x_CR_UARTEN))
2421 return;
2422
2423 lcr_h = pl011_read(uap, REG_LCRH_TX);
2424
2425 *parity = 'n';
2426 if (lcr_h & UART01x_LCRH_PEN) {
2427 if (lcr_h & UART01x_LCRH_EPS)
2428 *parity = 'e';
2429 else
2430 *parity = 'o';
2431 }
2432
2433 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2434 *bits = 7;
2435 else
2436 *bits = 8;
2437
2438 ibrd = pl011_read(uap, REG_IBRD);
2439 fbrd = pl011_read(uap, REG_FBRD);
2440
2441 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2442
2443 if (uap->vendor->oversampling &&
2444 (pl011_read(uap, REG_CR) & ST_UART011_CR_OVSFACT))
2445 *baud *= 2;
2446 }
2447
pl011_console_setup(struct console * co,char * options)2448 static int pl011_console_setup(struct console *co, char *options)
2449 {
2450 struct uart_amba_port *uap;
2451 int baud = 38400;
2452 int bits = 8;
2453 int parity = 'n';
2454 int flow = 'n';
2455 int ret;
2456
2457 /*
2458 * Check whether an invalid uart number has been specified, and
2459 * if so, search for the first available port that does have
2460 * console support.
2461 */
2462 if (co->index >= UART_NR)
2463 co->index = 0;
2464 uap = amba_ports[co->index];
2465 if (!uap)
2466 return -ENODEV;
2467
2468 /* Allow pins to be muxed in and configured */
2469 pinctrl_pm_select_default_state(uap->port.dev);
2470
2471 ret = clk_prepare(uap->clk);
2472 if (ret)
2473 return ret;
2474
2475 if (dev_get_platdata(uap->port.dev)) {
2476 struct amba_pl011_data *plat;
2477
2478 plat = dev_get_platdata(uap->port.dev);
2479 if (plat->init)
2480 plat->init();
2481 }
2482
2483 uap->port.uartclk = clk_get_rate(uap->clk);
2484
2485 if (uap->vendor->fixed_options) {
2486 baud = uap->fixed_baud;
2487 } else {
2488 if (options)
2489 uart_parse_options(options,
2490 &baud, &parity, &bits, &flow);
2491 else
2492 pl011_console_get_options(uap, &baud, &parity, &bits);
2493 }
2494
2495 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2496 }
2497
2498 /**
2499 * pl011_console_match - non-standard console matching
2500 * @co: registering console
2501 * @name: name from console command line
2502 * @idx: index from console command line
2503 * @options: ptr to option string from console command line
2504 *
2505 * Only attempts to match console command lines of the form:
2506 * console=pl011,mmio|mmio32,<addr>[,<options>]
2507 * console=pl011,0x<addr>[,<options>]
2508 * This form is used to register an initial earlycon boot console and
2509 * replace it with the amba_console at pl011 driver init.
2510 *
2511 * Performs console setup for a match (as required by interface)
2512 * If no <options> are specified, then assume the h/w is already setup.
2513 *
2514 * Returns 0 if console matches; otherwise non-zero to use default matching
2515 */
pl011_console_match(struct console * co,char * name,int idx,char * options)2516 static int pl011_console_match(struct console *co, char *name, int idx,
2517 char *options)
2518 {
2519 unsigned char iotype;
2520 resource_size_t addr;
2521 int i;
2522
2523 /*
2524 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2525 * have a distinct console name, so make sure we check for that.
2526 * The actual implementation of the erratum occurs in the probe
2527 * function.
2528 */
2529 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
2530 return -ENODEV;
2531
2532 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2533 return -ENODEV;
2534
2535 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2536 return -ENODEV;
2537
2538 /* try to match the port specified on the command line */
2539 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2540 struct uart_port *port;
2541
2542 if (!amba_ports[i])
2543 continue;
2544
2545 port = &amba_ports[i]->port;
2546
2547 if (port->mapbase != addr)
2548 continue;
2549
2550 co->index = i;
2551 uart_port_set_cons(port, co);
2552 return pl011_console_setup(co, options);
2553 }
2554
2555 return -ENODEV;
2556 }
2557
2558 static struct uart_driver amba_reg;
2559 static struct console amba_console = {
2560 .name = "ttyAMA",
2561 .write = pl011_console_write,
2562 .device = uart_console_device,
2563 .setup = pl011_console_setup,
2564 .match = pl011_console_match,
2565 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2566 .index = -1,
2567 .data = &amba_reg,
2568 };
2569
2570 #define AMBA_CONSOLE (&amba_console)
2571
qdf2400_e44_putc(struct uart_port * port,unsigned char c)2572 static void qdf2400_e44_putc(struct uart_port *port, unsigned char c)
2573 {
2574 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2575 cpu_relax();
2576 writel(c, port->membase + UART01x_DR);
2577 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2578 cpu_relax();
2579 }
2580
qdf2400_e44_early_write(struct console * con,const char * s,unsigned int n)2581 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned int n)
2582 {
2583 struct earlycon_device *dev = con->data;
2584
2585 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2586 }
2587
pl011_putc(struct uart_port * port,unsigned char c)2588 static void pl011_putc(struct uart_port *port, unsigned char c)
2589 {
2590 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2591 cpu_relax();
2592 if (port->iotype == UPIO_MEM32)
2593 writel(c, port->membase + UART01x_DR);
2594 else
2595 writeb(c, port->membase + UART01x_DR);
2596 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2597 cpu_relax();
2598 }
2599
pl011_early_write(struct console * con,const char * s,unsigned int n)2600 static void pl011_early_write(struct console *con, const char *s, unsigned int n)
2601 {
2602 struct earlycon_device *dev = con->data;
2603
2604 uart_console_write(&dev->port, s, n, pl011_putc);
2605 }
2606
2607 #ifdef CONFIG_CONSOLE_POLL
pl011_getc(struct uart_port * port)2608 static int pl011_getc(struct uart_port *port)
2609 {
2610 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE)
2611 return NO_POLL_CHAR;
2612
2613 if (port->iotype == UPIO_MEM32)
2614 return readl(port->membase + UART01x_DR);
2615 else
2616 return readb(port->membase + UART01x_DR);
2617 }
2618
pl011_early_read(struct console * con,char * s,unsigned int n)2619 static int pl011_early_read(struct console *con, char *s, unsigned int n)
2620 {
2621 struct earlycon_device *dev = con->data;
2622 int ch, num_read = 0;
2623
2624 while (num_read < n) {
2625 ch = pl011_getc(&dev->port);
2626 if (ch == NO_POLL_CHAR)
2627 break;
2628
2629 s[num_read++] = ch;
2630 }
2631
2632 return num_read;
2633 }
2634 #else
2635 #define pl011_early_read NULL
2636 #endif
2637
2638 /*
2639 * On non-ACPI systems, earlycon is enabled by specifying
2640 * "earlycon=pl011,<address>" on the kernel command line.
2641 *
2642 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2643 * by specifying only "earlycon" on the command line. Because it requires
2644 * SPCR, the console starts after ACPI is parsed, which is later than a
2645 * traditional early console.
2646 *
2647 * To get the traditional early console that starts before ACPI is parsed,
2648 * specify the full "earlycon=pl011,<address>" option.
2649 */
pl011_early_console_setup(struct earlycon_device * device,const char * opt)2650 static int __init pl011_early_console_setup(struct earlycon_device *device,
2651 const char *opt)
2652 {
2653 if (!device->port.membase)
2654 return -ENODEV;
2655
2656 device->con->write = pl011_early_write;
2657 device->con->read = pl011_early_read;
2658
2659 return 0;
2660 }
2661
2662 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2663
2664 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2665
2666 /*
2667 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2668 * Erratum 44, traditional earlycon can be enabled by specifying
2669 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2670 *
2671 * Alternatively, you can just specify "earlycon", and the early console
2672 * will be enabled with the information from the SPCR table. In this
2673 * case, the SPCR code will detect the need for the E44 work-around,
2674 * and set the console name to "qdf2400_e44".
2675 */
2676 static int __init
qdf2400_e44_early_console_setup(struct earlycon_device * device,const char * opt)2677 qdf2400_e44_early_console_setup(struct earlycon_device *device,
2678 const char *opt)
2679 {
2680 if (!device->port.membase)
2681 return -ENODEV;
2682
2683 device->con->write = qdf2400_e44_early_write;
2684 return 0;
2685 }
2686
2687 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
2688
2689 #else
2690 #define AMBA_CONSOLE NULL
2691 #endif
2692
2693 static struct uart_driver amba_reg = {
2694 .owner = THIS_MODULE,
2695 .driver_name = "ttyAMA",
2696 .dev_name = "ttyAMA",
2697 .major = SERIAL_AMBA_MAJOR,
2698 .minor = SERIAL_AMBA_MINOR,
2699 .nr = UART_NR,
2700 .cons = AMBA_CONSOLE,
2701 };
2702
pl011_probe_dt_alias(int index,struct device * dev)2703 static int pl011_probe_dt_alias(int index, struct device *dev)
2704 {
2705 struct device_node *np;
2706 static bool seen_dev_with_alias;
2707 static bool seen_dev_without_alias;
2708 int ret = index;
2709
2710 if (!IS_ENABLED(CONFIG_OF))
2711 return ret;
2712
2713 np = dev->of_node;
2714 if (!np)
2715 return ret;
2716
2717 ret = of_alias_get_id(np, "serial");
2718 if (ret < 0) {
2719 seen_dev_without_alias = true;
2720 ret = index;
2721 } else {
2722 seen_dev_with_alias = true;
2723 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret]) {
2724 dev_warn(dev, "requested serial port %d not available.\n", ret);
2725 ret = index;
2726 }
2727 }
2728
2729 if (seen_dev_with_alias && seen_dev_without_alias)
2730 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2731
2732 return ret;
2733 }
2734
2735 /* unregisters the driver also if no more ports are left */
pl011_unregister_port(struct uart_amba_port * uap)2736 static void pl011_unregister_port(struct uart_amba_port *uap)
2737 {
2738 int i;
2739 bool busy = false;
2740
2741 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2742 if (amba_ports[i] == uap)
2743 amba_ports[i] = NULL;
2744 else if (amba_ports[i])
2745 busy = true;
2746 }
2747 pl011_dma_remove(uap);
2748 if (!busy)
2749 uart_unregister_driver(&amba_reg);
2750 }
2751
pl011_find_free_port(void)2752 static int pl011_find_free_port(void)
2753 {
2754 int i;
2755
2756 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2757 if (!amba_ports[i])
2758 return i;
2759
2760 return -EBUSY;
2761 }
2762
pl011_setup_port(struct device * dev,struct uart_amba_port * uap,struct resource * mmiobase,int index)2763 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2764 struct resource *mmiobase, int index)
2765 {
2766 void __iomem *base;
2767 int ret;
2768
2769 base = devm_ioremap_resource(dev, mmiobase);
2770 if (IS_ERR(base))
2771 return PTR_ERR(base);
2772
2773 index = pl011_probe_dt_alias(index, dev);
2774
2775 uap->port.dev = dev;
2776 uap->port.mapbase = mmiobase->start;
2777 uap->port.membase = base;
2778 uap->port.fifosize = uap->fifosize;
2779 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE);
2780 uap->port.flags = UPF_BOOT_AUTOCONF;
2781 uap->port.line = index;
2782
2783 ret = uart_get_rs485_mode(&uap->port);
2784 if (ret)
2785 return ret;
2786
2787 amba_ports[index] = uap;
2788
2789 return 0;
2790 }
2791
pl011_register_port(struct uart_amba_port * uap)2792 static int pl011_register_port(struct uart_amba_port *uap)
2793 {
2794 int ret, i;
2795
2796 /* Ensure interrupts from this UART are masked and cleared */
2797 pl011_write(0, uap, REG_IMSC);
2798 pl011_write(0xffff, uap, REG_ICR);
2799
2800 if (!amba_reg.state) {
2801 ret = uart_register_driver(&amba_reg);
2802 if (ret < 0) {
2803 dev_err(uap->port.dev,
2804 "Failed to register AMBA-PL011 driver\n");
2805 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2806 if (amba_ports[i] == uap)
2807 amba_ports[i] = NULL;
2808 return ret;
2809 }
2810 }
2811
2812 ret = uart_add_one_port(&amba_reg, &uap->port);
2813 if (ret)
2814 pl011_unregister_port(uap);
2815
2816 return ret;
2817 }
2818
2819 static const struct serial_rs485 pl011_rs485_supported = {
2820 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2821 SER_RS485_RX_DURING_TX,
2822 .delay_rts_before_send = 1,
2823 .delay_rts_after_send = 1,
2824 };
2825
pl011_probe(struct amba_device * dev,const struct amba_id * id)2826 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2827 {
2828 struct uart_amba_port *uap;
2829 struct vendor_data *vendor = id->data;
2830 int portnr, ret;
2831 u32 val;
2832
2833 portnr = pl011_find_free_port();
2834 if (portnr < 0)
2835 return portnr;
2836
2837 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2838 GFP_KERNEL);
2839 if (!uap)
2840 return -ENOMEM;
2841
2842 uap->clk = devm_clk_get(&dev->dev, NULL);
2843 if (IS_ERR(uap->clk))
2844 return PTR_ERR(uap->clk);
2845
2846 uap->reg_offset = vendor->reg_offset;
2847 uap->vendor = vendor;
2848 uap->fifosize = vendor->get_fifosize(dev);
2849 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2850 uap->port.irq = dev->irq[0];
2851 uap->port.ops = &amba_pl011_pops;
2852 uap->port.rs485_config = pl011_rs485_config;
2853 uap->port.rs485_supported = pl011_rs485_supported;
2854 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2855
2856 if (device_property_read_u32(&dev->dev, "reg-io-width", &val) == 0) {
2857 switch (val) {
2858 case 1:
2859 uap->port.iotype = UPIO_MEM;
2860 break;
2861 case 4:
2862 uap->port.iotype = UPIO_MEM32;
2863 break;
2864 default:
2865 dev_warn(&dev->dev, "unsupported reg-io-width (%d)\n",
2866 val);
2867 return -EINVAL;
2868 }
2869 }
2870
2871 hrtimer_init(&uap->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2872 hrtimer_init(&uap->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2873 uap->trigger_start_tx.function = pl011_trigger_start_tx;
2874 uap->trigger_stop_tx.function = pl011_trigger_stop_tx;
2875
2876 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2877 if (ret)
2878 return ret;
2879
2880 amba_set_drvdata(dev, uap);
2881
2882 return pl011_register_port(uap);
2883 }
2884
pl011_remove(struct amba_device * dev)2885 static void pl011_remove(struct amba_device *dev)
2886 {
2887 struct uart_amba_port *uap = amba_get_drvdata(dev);
2888
2889 uart_remove_one_port(&amba_reg, &uap->port);
2890 pl011_unregister_port(uap);
2891 }
2892
2893 #ifdef CONFIG_PM_SLEEP
pl011_suspend(struct device * dev)2894 static int pl011_suspend(struct device *dev)
2895 {
2896 struct uart_amba_port *uap = dev_get_drvdata(dev);
2897
2898 if (!uap)
2899 return -EINVAL;
2900
2901 return uart_suspend_port(&amba_reg, &uap->port);
2902 }
2903
pl011_resume(struct device * dev)2904 static int pl011_resume(struct device *dev)
2905 {
2906 struct uart_amba_port *uap = dev_get_drvdata(dev);
2907
2908 if (!uap)
2909 return -EINVAL;
2910
2911 return uart_resume_port(&amba_reg, &uap->port);
2912 }
2913 #endif
2914
2915 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2916
2917 #ifdef CONFIG_ACPI_SPCR_TABLE
qpdf2400_erratum44_workaround(struct device * dev,struct uart_amba_port * uap)2918 static void qpdf2400_erratum44_workaround(struct device *dev,
2919 struct uart_amba_port *uap)
2920 {
2921 if (!qdf2400_e44_present)
2922 return;
2923
2924 dev_info(dev, "working around QDF2400 SoC erratum 44\n");
2925 uap->vendor = &vendor_qdt_qdf2400_e44;
2926 }
2927 #else
qpdf2400_erratum44_workaround(struct device * dev,struct uart_amba_port * uap)2928 static void qpdf2400_erratum44_workaround(struct device *dev,
2929 struct uart_amba_port *uap)
2930 { /* empty */ }
2931 #endif
2932
sbsa_uart_probe(struct platform_device * pdev)2933 static int sbsa_uart_probe(struct platform_device *pdev)
2934 {
2935 struct uart_amba_port *uap;
2936 struct resource *r;
2937 int portnr, ret;
2938 int baudrate;
2939
2940 /*
2941 * Check the mandatory baud rate parameter in the DT node early
2942 * so that we can easily exit with the error.
2943 */
2944 if (pdev->dev.of_node) {
2945 struct device_node *np = pdev->dev.of_node;
2946
2947 ret = of_property_read_u32(np, "current-speed", &baudrate);
2948 if (ret)
2949 return ret;
2950 } else {
2951 baudrate = 115200;
2952 }
2953
2954 portnr = pl011_find_free_port();
2955 if (portnr < 0)
2956 return portnr;
2957
2958 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2959 GFP_KERNEL);
2960 if (!uap)
2961 return -ENOMEM;
2962
2963 ret = platform_get_irq(pdev, 0);
2964 if (ret < 0)
2965 return ret;
2966 uap->port.irq = ret;
2967
2968 uap->vendor = &vendor_sbsa;
2969 qpdf2400_erratum44_workaround(&pdev->dev, uap);
2970
2971 uap->reg_offset = uap->vendor->reg_offset;
2972 uap->fifosize = 32;
2973 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2974 uap->port.ops = &sbsa_uart_pops;
2975 uap->fixed_baud = baudrate;
2976
2977 snprintf(uap->type, sizeof(uap->type), "SBSA");
2978
2979 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2980
2981 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2982 if (ret)
2983 return ret;
2984
2985 platform_set_drvdata(pdev, uap);
2986
2987 return pl011_register_port(uap);
2988 }
2989
sbsa_uart_remove(struct platform_device * pdev)2990 static void sbsa_uart_remove(struct platform_device *pdev)
2991 {
2992 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2993
2994 uart_remove_one_port(&amba_reg, &uap->port);
2995 pl011_unregister_port(uap);
2996 }
2997
2998 static const struct of_device_id sbsa_uart_of_match[] = {
2999 { .compatible = "arm,sbsa-uart", },
3000 {},
3001 };
3002 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
3003
3004 static const struct acpi_device_id __maybe_unused sbsa_uart_acpi_match[] = {
3005 { "ARMH0011", 0 },
3006 { "ARMHB000", 0 },
3007 {},
3008 };
3009 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
3010
3011 static struct platform_driver arm_sbsa_uart_platform_driver = {
3012 .probe = sbsa_uart_probe,
3013 .remove = sbsa_uart_remove,
3014 .driver = {
3015 .name = "sbsa-uart",
3016 .pm = &pl011_dev_pm_ops,
3017 .of_match_table = of_match_ptr(sbsa_uart_of_match),
3018 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
3019 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
3020 },
3021 };
3022
3023 static const struct amba_id pl011_ids[] = {
3024 {
3025 .id = 0x00041011,
3026 .mask = 0x000fffff,
3027 .data = &vendor_arm,
3028 },
3029 {
3030 .id = 0x00380802,
3031 .mask = 0x00ffffff,
3032 .data = &vendor_st,
3033 },
3034 { 0, 0 },
3035 };
3036
3037 MODULE_DEVICE_TABLE(amba, pl011_ids);
3038
3039 static struct amba_driver pl011_driver = {
3040 .drv = {
3041 .name = "uart-pl011",
3042 .pm = &pl011_dev_pm_ops,
3043 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
3044 },
3045 .id_table = pl011_ids,
3046 .probe = pl011_probe,
3047 .remove = pl011_remove,
3048 };
3049
pl011_init(void)3050 static int __init pl011_init(void)
3051 {
3052 pr_info("Serial: AMBA PL011 UART driver\n");
3053
3054 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
3055 pr_warn("could not register SBSA UART platform driver\n");
3056 return amba_driver_register(&pl011_driver);
3057 }
3058
pl011_exit(void)3059 static void __exit pl011_exit(void)
3060 {
3061 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
3062 amba_driver_unregister(&pl011_driver);
3063 }
3064
3065 /*
3066 * While this can be a module, if builtin it's most likely the console
3067 * So let's leave module_exit but move module_init to an earlier place
3068 */
3069 arch_initcall(pl011_init);
3070 module_exit(pl011_exit);
3071
3072 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
3073 MODULE_DESCRIPTION("ARM AMBA serial port driver");
3074 MODULE_LICENSE("GPL");
3075