Lines Matching +full:uart +full:- +full:fifosize
1 // SPDX-License-Identifier: GPL-2.0
37 /* Set the max number of UART port
243 * struct pch_uart_driver_data - private data structure for UART-DMA
244 * @port_type: The type of UART port
245 * @line_no: UART port line number (0, 1, 2...)
296 struct eg20t_port *priv = file->private_data; in port_show_regs()
306 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
307 "PCH EG20T port[%d] regs:\n", priv->port.line); in port_show_regs()
309 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
311 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
312 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); in port_show_regs()
313 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
314 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); in port_show_regs()
315 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
316 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); in port_show_regs()
317 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
318 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); in port_show_regs()
319 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
320 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); in port_show_regs()
321 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
322 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); in port_show_regs()
323 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
325 ioread8(priv->membase + PCH_UART_BRCSR)); in port_show_regs()
327 lcr = ioread8(priv->membase + UART_LCR); in port_show_regs()
328 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); in port_show_regs()
329 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
330 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); in port_show_regs()
331 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, in port_show_regs()
332 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); in port_show_regs()
333 iowrite8(lcr, priv->membase + UART_LCR); in port_show_regs()
352 .ident = "CM-iTC",
354 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
373 .ident = "COMe-mTT",
375 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
380 .ident = "nanoETXexpress-TT",
382 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
396 /* Return UART clock, checking for board specific clocks. */
406 return (unsigned long)d->driver_data; in pch_uart_get_uartclk()
414 u8 ier = ioread8(priv->membase + UART_IER); in pch_uart_hal_enable_interrupt()
416 iowrite8(ier, priv->membase + UART_IER); in pch_uart_hal_enable_interrupt()
422 u8 ier = ioread8(priv->membase + UART_IER); in pch_uart_hal_disable_interrupt()
424 iowrite8(ier, priv->membase + UART_IER); in pch_uart_hal_disable_interrupt()
434 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); in pch_uart_hal_set_line()
436 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); in pch_uart_hal_set_line()
437 return -EINVAL; in pch_uart_hal_set_line()
444 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); in pch_uart_hal_set_line()
445 return -EINVAL; in pch_uart_hal_set_line()
449 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); in pch_uart_hal_set_line()
450 return -EINVAL; in pch_uart_hal_set_line()
454 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); in pch_uart_hal_set_line()
455 return -EINVAL; in pch_uart_hal_set_line()
462 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n", in pch_uart_hal_set_line()
464 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); in pch_uart_hal_set_line()
465 iowrite8(dll, priv->membase + PCH_UART_DLL); in pch_uart_hal_set_line()
466 iowrite8(dlm, priv->membase + PCH_UART_DLM); in pch_uart_hal_set_line()
467 iowrite8(lcr, priv->membase + UART_LCR); in pch_uart_hal_set_line()
476 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", in pch_uart_hal_fifo_reset()
478 return -EINVAL; in pch_uart_hal_fifo_reset()
481 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); in pch_uart_hal_fifo_reset()
482 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, in pch_uart_hal_fifo_reset()
483 priv->membase + UART_FCR); in pch_uart_hal_fifo_reset()
484 iowrite8(priv->fcr, priv->membase + UART_FCR); in pch_uart_hal_fifo_reset()
496 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", in pch_uart_hal_set_fifo()
498 return -EINVAL; in pch_uart_hal_set_fifo()
502 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", in pch_uart_hal_set_fifo()
504 return -EINVAL; in pch_uart_hal_set_fifo()
508 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", in pch_uart_hal_set_fifo()
510 return -EINVAL; in pch_uart_hal_set_fifo()
513 switch (priv->fifo_size) { in pch_uart_hal_set_fifo()
515 priv->trigger_level = in pch_uart_hal_set_fifo()
519 priv->trigger_level = in pch_uart_hal_set_fifo()
523 priv->trigger_level = in pch_uart_hal_set_fifo()
527 priv->trigger_level = in pch_uart_hal_set_fifo()
533 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); in pch_uart_hal_set_fifo()
535 priv->membase + UART_FCR); in pch_uart_hal_set_fifo()
536 iowrite8(fcr, priv->membase + UART_FCR); in pch_uart_hal_set_fifo()
537 priv->fcr = fcr; in pch_uart_hal_set_fifo()
544 unsigned int msr = ioread8(priv->membase + UART_MSR); in pch_uart_hal_get_modem()
545 priv->dmsr = msr & PCH_UART_MSR_DELTA; in pch_uart_hal_get_modem()
554 struct uart_port *port = &priv->port; in pch_uart_hal_read()
556 lsr = ioread8(priv->membase + UART_LSR); in pch_uart_hal_read()
557 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); in pch_uart_hal_read()
559 lsr = ioread8(priv->membase + UART_LSR)) { in pch_uart_hal_read()
560 rbr = ioread8(priv->membase + PCH_UART_RBR); in pch_uart_hal_read()
563 port->icount.brk++; in pch_uart_hal_read()
577 return ioread8(priv->membase + UART_IIR) &\ in pch_uart_hal_get_iid()
583 return ioread8(priv->membase + UART_LSR); in pch_uart_hal_get_line_status()
590 lcr = ioread8(priv->membase + UART_LCR); in pch_uart_hal_set_break()
596 iowrite8(lcr, priv->membase + UART_LCR); in pch_uart_hal_set_break()
602 struct uart_port *port = &priv->port; in push_rx()
603 struct tty_port *tport = &port->state->port; in push_rx()
612 struct uart_port *port = &priv->port; in dma_push_rx()
613 struct tty_port *tport = &port->state->port; in dma_push_rx()
618 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", in dma_push_rx()
619 size - room); in dma_push_rx()
623 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size); in dma_push_rx()
625 port->icount.rx += room; in dma_push_rx()
635 if (priv->chan_tx) { in pch_free_dma()
636 dma_release_channel(priv->chan_tx); in pch_free_dma()
637 priv->chan_tx = NULL; in pch_free_dma()
639 if (priv->chan_rx) { in pch_free_dma()
640 dma_release_channel(priv->chan_rx); in pch_free_dma()
641 priv->chan_rx = NULL; in pch_free_dma()
644 if (priv->rx_buf_dma) { in pch_free_dma()
645 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, in pch_free_dma()
646 priv->rx_buf_dma); in pch_free_dma()
647 priv->rx_buf_virt = NULL; in pch_free_dma()
648 priv->rx_buf_dma = 0; in pch_free_dma()
658 if ((chan->chan_id == param->chan_id) && (param->dma_dev == in filter()
659 chan->device->dev)) { in filter()
660 chan->private = param; in filter()
679 dma_dev = pci_get_slot(priv->pdev->bus, in pch_request_dma()
680 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0)); in pch_request_dma()
683 param = &priv->param_tx; in pch_request_dma()
684 param->dma_dev = &dma_dev->dev; in pch_request_dma()
685 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ in pch_request_dma()
687 param->tx_reg = port->mapbase + UART_TX; in pch_request_dma()
690 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", in pch_request_dma()
695 priv->chan_tx = chan; in pch_request_dma()
698 param = &priv->param_rx; in pch_request_dma()
699 param->dma_dev = &dma_dev->dev; in pch_request_dma()
700 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ in pch_request_dma()
702 param->rx_reg = port->mapbase + UART_RX; in pch_request_dma()
705 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", in pch_request_dma()
707 dma_release_channel(priv->chan_tx); in pch_request_dma()
708 priv->chan_tx = NULL; in pch_request_dma()
714 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, in pch_request_dma()
715 &priv->rx_buf_dma, GFP_KERNEL); in pch_request_dma()
716 priv->chan_rx = chan; in pch_request_dma()
724 struct uart_port *port = &priv->port; in pch_dma_rx_complete()
727 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); in pch_dma_rx_complete()
728 count = dma_push_rx(priv, priv->trigger_level); in pch_dma_rx_complete()
730 tty_flip_buffer_push(&port->state->port); in pch_dma_rx_complete()
731 async_tx_ack(priv->desc_rx); in pch_dma_rx_complete()
739 struct uart_port *port = &priv->port; in pch_dma_tx_complete()
740 struct scatterlist *sg = priv->sg_tx_p; in pch_dma_tx_complete()
743 for (i = 0; i < priv->nent; i++, sg++) in pch_dma_tx_complete()
746 async_tx_ack(priv->desc_tx); in pch_dma_tx_complete()
747 dma_unmap_sg(port->dev, priv->sg_tx_p, priv->orig_nent, DMA_TO_DEVICE); in pch_dma_tx_complete()
748 priv->tx_dma_use = 0; in pch_dma_tx_complete()
749 priv->nent = 0; in pch_dma_tx_complete()
750 priv->orig_nent = 0; in pch_dma_tx_complete()
751 kfree(priv->sg_tx_p); in pch_dma_tx_complete()
760 if (!priv->start_rx) { in handle_rx_to()
765 buf = &priv->rxbuf; in handle_rx_to()
767 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); in handle_rx_to()
768 push_rx(priv, buf->buf, rx_size); in handle_rx_to()
769 } while (rx_size == buf->size); in handle_rx_to()
776 struct uart_port *port = &priv->port; in dma_handle_rx()
781 sg = &priv->sg_rx; in dma_handle_rx()
783 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ in dma_handle_rx()
785 sg_dma_len(sg) = priv->trigger_level; in dma_handle_rx()
787 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), in dma_handle_rx()
788 sg_dma_len(sg), offset_in_page(priv->rx_buf_virt)); in dma_handle_rx()
790 sg_dma_address(sg) = priv->rx_buf_dma; in dma_handle_rx()
792 desc = dmaengine_prep_slave_sg(priv->chan_rx, in dma_handle_rx()
799 priv->desc_rx = desc; in dma_handle_rx()
800 desc->callback = pch_dma_rx_complete; in dma_handle_rx()
801 desc->callback_param = priv; in dma_handle_rx()
802 desc->tx_submit(desc); in dma_handle_rx()
803 dma_async_issue_pending(priv->chan_rx); in dma_handle_rx()
810 struct uart_port *port = &priv->port; in handle_tx()
815 if (!priv->start_tx) { in handle_tx()
816 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", in handle_tx()
819 priv->tx_empty = 1; in handle_tx()
823 fifo_size = max(priv->fifo_size, 1); in handle_tx()
825 if (port->x_char) { in handle_tx()
826 iowrite8(port->x_char, priv->membase + PCH_UART_THR); in handle_tx()
827 port->icount.tx++; in handle_tx()
828 port->x_char = 0; in handle_tx()
830 fifo_size--; in handle_tx()
835 iowrite8(ch, priv->membase + PCH_UART_THR); in handle_tx()
836 fifo_size--; in handle_tx()
840 priv->tx_empty = tx_empty; in handle_tx()
852 struct uart_port *port = &priv->port; in dma_handle_tx()
853 struct tty_port *tport = &port->state->port; in dma_handle_tx()
864 if (!priv->start_tx) { in dma_handle_tx()
865 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", in dma_handle_tx()
868 priv->tx_empty = 1; in dma_handle_tx()
872 if (priv->tx_dma_use) { in dma_handle_tx()
873 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", in dma_handle_tx()
876 priv->tx_empty = 1; in dma_handle_tx()
880 fifo_size = max(priv->fifo_size, 1); in dma_handle_tx()
882 if (port->x_char) { in dma_handle_tx()
883 iowrite8(port->x_char, priv->membase + PCH_UART_THR); in dma_handle_tx()
884 port->icount.tx++; in dma_handle_tx()
885 port->x_char = 0; in dma_handle_tx()
886 fifo_size--; in dma_handle_tx()
889 bytes = kfifo_out_linear(&tport->xmit_fifo, &tail, UART_XMIT_SIZE); in dma_handle_tx()
891 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); in dma_handle_tx()
907 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", in dma_handle_tx()
910 priv->tx_dma_use = 1; in dma_handle_tx()
912 priv->sg_tx_p = kmalloc_array(num, sizeof(struct scatterlist), GFP_ATOMIC); in dma_handle_tx()
913 if (!priv->sg_tx_p) { in dma_handle_tx()
914 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__); in dma_handle_tx()
918 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ in dma_handle_tx()
919 sg = priv->sg_tx_p; in dma_handle_tx()
922 if (i == (num - 1)) in dma_handle_tx()
923 sg_set_page(sg, virt_to_page(tport->xmit_buf), in dma_handle_tx()
926 sg_set_page(sg, virt_to_page(tport->xmit_buf), in dma_handle_tx()
930 sg = priv->sg_tx_p; in dma_handle_tx()
931 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); in dma_handle_tx()
933 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); in dma_handle_tx()
936 priv->orig_nent = num; in dma_handle_tx()
937 priv->nent = nent; in dma_handle_tx()
940 sg->offset = tail + fifo_size * i; in dma_handle_tx()
942 ~(UART_XMIT_SIZE - 1)) + sg->offset; in dma_handle_tx()
943 if (i == (nent - 1)) in dma_handle_tx()
949 desc = dmaengine_prep_slave_sg(priv->chan_tx, in dma_handle_tx()
950 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, in dma_handle_tx()
953 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n", in dma_handle_tx()
957 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); in dma_handle_tx()
958 priv->desc_tx = desc; in dma_handle_tx()
959 desc->callback = pch_dma_tx_complete; in dma_handle_tx()
960 desc->callback_param = priv; in dma_handle_tx()
962 desc->tx_submit(desc); in dma_handle_tx()
964 dma_async_issue_pending(priv->chan_tx); in dma_handle_tx()
971 struct uart_port *port = &priv->port; in pch_uart_err_ir()
972 struct tty_struct *tty = tty_port_tty_get(&port->state->port); in pch_uart_err_ir()
980 port->icount.frame++; in pch_uart_err_ir()
985 port->icount.parity++; in pch_uart_err_ir()
990 port->icount.overrun++; in pch_uart_err_ir()
996 dev_err(&priv->pdev->dev, error_msg[i]); in pch_uart_err_ir()
1012 uart_port_lock(&priv->port); in pch_uart_interrupt()
1030 if (priv->use_dma) { in pch_uart_interrupt()
1049 if (priv->use_dma) in pch_uart_interrupt()
1063 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, in pch_uart_interrupt()
1065 ret = -1; in pch_uart_interrupt()
1072 uart_unlock_and_check_sysrq(&priv->port); in pch_uart_interrupt()
1083 if (priv->tx_empty) in pch_uart_tx_empty()
1126 if (priv->mcr & UART_MCR_AFE) in pch_uart_set_mctrl()
1130 iowrite8(mcr, priv->membase + UART_MCR); in pch_uart_set_mctrl()
1137 priv->start_tx = 0; in pch_uart_stop_tx()
1138 priv->tx_dma_use = 0; in pch_uart_stop_tx()
1147 if (priv->use_dma) { in pch_uart_start_tx()
1148 if (priv->tx_dma_use) { in pch_uart_start_tx()
1149 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", in pch_uart_start_tx()
1155 priv->start_tx = 1; in pch_uart_start_tx()
1163 priv->start_rx = 0; in pch_uart_stop_rx()
1183 uart_port_lock_irqsave(&priv->port, &flags); in pch_uart_break_ctl()
1185 uart_port_unlock_irqrestore(&priv->port, flags); in pch_uart_break_ctl()
1197 priv->tx_empty = 1; in pch_uart_startup()
1199 if (port->uartclk) in pch_uart_startup()
1200 priv->uartclk = port->uartclk; in pch_uart_startup()
1202 port->uartclk = priv->uartclk; in pch_uart_startup()
1211 switch (priv->fifo_size) { in pch_uart_startup()
1227 switch (priv->trigger) { in pch_uart_startup()
1232 trigger_level = priv->fifo_size / 4; in pch_uart_startup()
1235 trigger_level = priv->fifo_size / 2; in pch_uart_startup()
1239 trigger_level = priv->fifo_size - (priv->fifo_size / 8); in pch_uart_startup()
1243 priv->trigger_level = trigger_level; in pch_uart_startup()
1245 fifo_size, priv->trigger); in pch_uart_startup()
1249 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, in pch_uart_startup()
1250 priv->irq_name, priv); in pch_uart_startup()
1254 if (priv->use_dma) in pch_uart_startup()
1257 priv->start_rx = 1; in pch_uart_startup()
1276 dev_err(priv->port.dev, in pch_uart_shutdown()
1281 free_irq(priv->port.irq, priv); in pch_uart_shutdown()
1297 switch (termios->c_cflag & CSIZE) { in pch_uart_set_termios()
1311 if (termios->c_cflag & CSTOPB) in pch_uart_set_termios()
1316 if (termios->c_cflag & PARENB) { in pch_uart_set_termios()
1317 if (termios->c_cflag & PARODD) in pch_uart_set_termios()
1326 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) in pch_uart_set_termios()
1327 priv->mcr |= UART_MCR_AFE; in pch_uart_set_termios()
1329 priv->mcr &= ~UART_MCR_AFE; in pch_uart_set_termios()
1331 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ in pch_uart_set_termios()
1333 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); in pch_uart_set_termios()
1337 uart_update_timeout(port, termios->c_cflag, baud); in pch_uart_set_termios()
1342 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); in pch_uart_set_termios()
1361 pci_iounmap(priv->pdev, priv->membase); in pch_uart_release_port()
1362 pci_release_regions(priv->pdev); in pch_uart_release_port()
1372 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); in pch_uart_request_port()
1374 return -EBUSY; in pch_uart_request_port()
1376 membase = pci_iomap(priv->pdev, 1, 0); in pch_uart_request_port()
1378 pci_release_regions(priv->pdev); in pch_uart_request_port()
1379 return -EBUSY; in pch_uart_request_port()
1381 priv->membase = port->membase = membase; in pch_uart_request_port()
1392 port->type = priv->port_type; in pch_uart_config_port()
1403 if (serinfo->flags & UPF_LOW_LATENCY) { in pch_uart_verify_port()
1404 dev_info(priv->port.dev, in pch_uart_verify_port()
1405 "PCH UART : Use PIO Mode (without DMA)\n"); in pch_uart_verify_port()
1406 priv->use_dma = 0; in pch_uart_verify_port()
1407 serinfo->flags &= ~UPF_LOW_LATENCY; in pch_uart_verify_port()
1410 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", in pch_uart_verify_port()
1412 return -EOPNOTSUPP; in pch_uart_verify_port()
1414 if (!priv->use_dma) { in pch_uart_verify_port()
1416 if (priv->chan_rx) in pch_uart_verify_port()
1417 priv->use_dma = 1; in pch_uart_verify_port()
1419 dev_info(priv->port.dev, "PCH UART: %s\n", in pch_uart_verify_port()
1420 priv->use_dma ? in pch_uart_verify_port()
1437 status = ioread8(up->membase + UART_LSR); in wait_for_xmitr()
1441 if (--tmout == 0) in wait_for_xmitr()
1447 if (up->port.flags & UPF_CONS_FLOW) { in wait_for_xmitr()
1449 for (tmout = 1000000; tmout; tmout--) { in wait_for_xmitr()
1450 unsigned int msr = ioread8(up->membase + UART_MSR); in wait_for_xmitr()
1462 * Console polling routines for communicate via uart while
1469 u8 lsr = ioread8(priv->membase + UART_LSR); in pch_uart_get_poll_char()
1474 return ioread8(priv->membase + PCH_UART_RBR); in pch_uart_get_poll_char()
1488 ier = ioread8(priv->membase + UART_IER); in pch_uart_put_poll_char()
1495 iowrite8(c, priv->membase + PCH_UART_THR); in pch_uart_put_poll_char()
1502 iowrite8(ier, priv->membase + UART_IER); in pch_uart_put_poll_char()
1538 iowrite8(ch, priv->membase + PCH_UART_THR); in pch_console_putchar()
1555 priv = pch_uart_ports[co->index]; in pch_console_write()
1560 locked = uart_port_trylock_irqsave(&priv->port, &flags); in pch_console_write()
1562 uart_port_lock_irqsave(&priv->port, &flags); in pch_console_write()
1567 ier = ioread8(priv->membase + UART_IER); in pch_console_write()
1571 uart_console_write(&priv->port, s, count, pch_console_putchar); in pch_console_write()
1578 iowrite8(ier, priv->membase + UART_IER); in pch_console_write()
1581 uart_port_unlock_irqrestore(&priv->port, flags); in pch_console_write()
1593 * Check whether an invalid uart number has been specified, and in pch_console_setup()
1597 if (co->index >= PCH_UART_NR) in pch_console_setup()
1598 co->index = 0; in pch_console_setup()
1599 port = &pch_uart_ports[co->index]->port; in pch_console_setup()
1601 if (!port || (!port->iobase && !port->membase)) in pch_console_setup()
1602 return -ENODEV; in pch_console_setup()
1604 port->uartclk = pch_uart_get_uartclk(); in pch_console_setup()
1620 .index = -1,
1647 int fifosize; in pch_uart_init_port() local
1652 board = &drv_dat[id->driver_data]; in pch_uart_init_port()
1653 port_type = board->port_type; in pch_uart_init_port()
1665 fifosize = 256; /* EG20T/ML7213: UART0 */ in pch_uart_init_port()
1668 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ in pch_uart_init_port()
1671 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); in pch_uart_init_port()
1680 priv->mapbase = mapbase; in pch_uart_init_port()
1681 priv->iobase = iobase; in pch_uart_init_port()
1682 priv->pdev = pdev; in pch_uart_init_port()
1683 priv->tx_empty = 1; in pch_uart_init_port()
1684 priv->rxbuf.buf = rxbuf; in pch_uart_init_port()
1685 priv->rxbuf.size = PAGE_SIZE; in pch_uart_init_port()
1687 priv->fifo_size = fifosize; in pch_uart_init_port()
1688 priv->uartclk = pch_uart_get_uartclk(); in pch_uart_init_port()
1689 priv->port_type = port_type; in pch_uart_init_port()
1690 priv->port.dev = &pdev->dev; in pch_uart_init_port()
1691 priv->port.iobase = iobase; in pch_uart_init_port()
1692 priv->port.membase = NULL; in pch_uart_init_port()
1693 priv->port.mapbase = mapbase; in pch_uart_init_port()
1694 priv->port.irq = pdev->irq; in pch_uart_init_port()
1695 priv->port.iotype = UPIO_PORT; in pch_uart_init_port()
1696 priv->port.ops = &pch_uart_ops; in pch_uart_init_port()
1697 priv->port.flags = UPF_BOOT_AUTOCONF; in pch_uart_init_port()
1698 priv->port.fifosize = fifosize; in pch_uart_init_port()
1699 priv->port.line = board->line_no; in pch_uart_init_port()
1700 priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE); in pch_uart_init_port()
1701 priv->trigger = PCH_UART_HAL_TRIGGER_M; in pch_uart_init_port()
1703 snprintf(priv->irq_name, IRQ_NAME_SIZE, in pch_uart_init_port()
1705 priv->port.line); in pch_uart_init_port()
1708 priv->trigger_level = 1; in pch_uart_init_port()
1709 priv->fcr = 0; in pch_uart_init_port()
1711 if (pdev->dev.of_node) in pch_uart_init_port()
1712 of_property_read_u32(pdev->dev.of_node, "clock-frequency" in pch_uart_init_port()
1716 pch_uart_ports[board->line_no] = priv; in pch_uart_init_port()
1718 ret = uart_add_one_port(&pch_uart_driver, &priv->port); in pch_uart_init_port()
1722 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line); in pch_uart_init_port()
1730 pch_uart_ports[board->line_no] = NULL; in pch_uart_init_port()
1744 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line); in pch_uart_exit_port()
1746 uart_remove_one_port(&pch_uart_driver, &priv->port); in pch_uart_exit_port()
1747 free_page((unsigned long)priv->rxbuf.buf); in pch_uart_exit_port()
1757 pch_uart_ports[priv->port.line] = NULL; in pch_uart_pci_remove()
1769 uart_suspend_port(&pch_uart_driver, &priv->port); in pch_uart_pci_suspend()
1778 uart_resume_port(&pch_uart_driver, &priv->port); in pch_uart_pci_resume()
1821 ret = -EBUSY; in pch_uart_pci_probe()
1851 /* register as UART driver */ in pch_uart_module_init()
1873 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1881 "Override UART default or board specific UART clock");