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/linux-6.14.4/Documentation/devicetree/bindings/display/msm/
Dqcom,sm8450-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8450 Display MDSS
10 - Dmitry Baryshkov <[email protected]>
13 SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm8450-mdss
24 - description: Display AHB
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Ddsi-controller-main.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <[email protected]>
15 - items:
16 - enum:
17 - qcom,apq8064-dsi-ctrl
18 - qcom,msm8226-dsi-ctrl
19 - qcom,msm8916-dsi-ctrl
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Dqcom,sc7280-dpu.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <[email protected]>
11 - Neil Armstrong <[email protected]>
12 - Dmitry Baryshkov <[email protected]>
13 - Krishna Manikandan <[email protected]>
15 $ref: /schemas/display/msm/dpu-common.yaml#
20 - qcom,sc7280-dpu
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Ddp-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuogee Hsieh <[email protected]>
11 - Abhinav Kumar <[email protected]>
20 - enum:
21 - qcom,sa8775p-dp
22 - qcom,sc7180-dp
23 - qcom,sc7280-dp
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/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dsm8450.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
12 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
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Dsm8450-hdk.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9 #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
10 #include <dt-bindings/iio/qcom,spmi-adc7-pm8350b.h>
11 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
12 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
13 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
14 #include "sm8450.dtsi"
23 model = "Qualcomm Technologies, Inc. SM8450 HDK";
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Dsm8650-mtp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
21 compatible = "qcom,sm8650-mtp", "qcom,sm8650";
28 stdout-path = "serial0:115200n8";
31 pmic-glink {
32 compatible = "qcom,sm8650-pmic-glink",
33 "qcom,sm8550-pmic-glink",
34 "qcom,pmic-glink";
35 #address-cells = <1>;
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Dsm8550-mtp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
22 compatible = "qcom,sm8550-mtp", "qcom,sm8550";
23 chassis-type = "handset";
29 wcd938x: audio-codec {
30 compatible = "qcom,wcd9385-codec";
32 pinctrl-names = "default";
33 pinctrl-0 = <&wcd_default>;
35 qcom,micbias1-microvolt = <1800000>;
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Dsm8550-qrd.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
23 compatible = "qcom,sm8550-qrd", "qcom,sm8550";
24 chassis-type = "handset";
31 wcd938x: audio-codec {
32 compatible = "qcom,wcd9385-codec";
34 pinctrl-names = "default";
35 pinctrl-0 = <&wcd_default>;
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Dsm8650-qrd.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
22 compatible = "qcom,sm8650-qrd", "qcom,sm8650";
30 stdout-path = "serial0:115200n8";
33 gpio-keys {
34 compatible = "gpio-keys";
36 pinctrl-0 = <&volume_up_n>;
37 pinctrl-names = "default";
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Dsm8550-hdk.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
22 compatible = "qcom,sm8550-hdk", "qcom,sm8550";
23 chassis-type = "embedded";
30 wcd938x: audio-codec {
31 compatible = "qcom,wcd9385-codec";
33 pinctrl-names = "default";
34 pinctrl-0 = <&wcd_default>;
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Dsm8650-hdk.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
21 compatible = "qcom,sm8650-hdk", "qcom,sm8650";
22 chassis-type = "embedded";
30 stdout-path = "serial0:115200n8";
33 hdmi-out {
34 compatible = "hdmi-connector";
39 remote-endpoint = <&lt9611_out>;
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Dsm8550.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
8 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
9 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
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/linux-6.14.4/drivers/gpu/drm/msm/
Dmsm_mdss.c2 * SPDX-License-Identifier: GPL-2.0
22 #include <generated/mdss.xml.h>
26 #define DEFAULT_REG_BW 153600 /* Used in mdss fbdev driver */
52 path0 = devm_of_icc_get(dev, "mdp0-mem"); in msm_mdss_parse_data_bus_icc_path()
56 msm_mdss->mdp_path[0] = path0; in msm_mdss_parse_data_bus_icc_path()
57 msm_mdss->num_mdp_paths = 1; in msm_mdss_parse_data_bus_icc_path()
59 path1 = devm_of_icc_get(dev, "mdp1-mem"); in msm_mdss_parse_data_bus_icc_path()
61 msm_mdss->mdp_path[1] = path1; in msm_mdss_parse_data_bus_icc_path()
62 msm_mdss->num_mdp_paths++; in msm_mdss_parse_data_bus_icc_path()
65 reg_bus_path = of_icc_get(dev, "cpu-cfg"); in msm_mdss_parse_data_bus_icc_path()
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/linux-6.14.4/drivers/iommu/arm/arm-smmu/
Darm-smmu-qcom.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
14 #include "arm-smmu.h"
15 #include "arm-smmu-qcom.h"
17 #define QCOM_DUMMY_VAL -1
20 * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching in the
38 { .compatible = "qcom,adreno-gmu",
40 { .compatible = "qcom,adreno-smmu",
44 { .compatible = "qcom,sc7280-mdss",
46 { .compatible = "qcom,sc7280-venus",
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/linux-6.14.4/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_kms.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
13 #include <linux/dma-buf.h>
65 struct dpu_kms *kms = s->private; in _dpu_danger_signal_status()
68 if (!kms->hw_mdp) { in _dpu_danger_signal_status()
75 pm_runtime_get_sync(&kms->pdev->dev); in _dpu_danger_signal_status()
78 if (kms->hw_mdp->ops.get_danger_status) in _dpu_danger_signal_status()
79 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, in _dpu_danger_signal_status()
83 if (kms->hw_mdp->ops.get_safe_status) in _dpu_danger_signal_status()
84 kms->hw_mdp->ops.get_safe_status(kms->hw_mdp, in _dpu_danger_signal_status()
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