1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MSM Display Port Controller
8
9maintainers:
10  - Kuogee Hsieh <[email protected]>
11  - Abhinav Kumar <[email protected]>
12
13description: |
14  Device tree bindings for DisplayPort host controller for MSM targets
15  that are compatible with VESA DisplayPort interface specification.
16
17properties:
18  compatible:
19    oneOf:
20      - enum:
21          - qcom,sa8775p-dp
22          - qcom,sc7180-dp
23          - qcom,sc7280-dp
24          - qcom,sc7280-edp
25          - qcom,sc8180x-dp
26          - qcom,sc8180x-edp
27          - qcom,sc8280xp-dp
28          - qcom,sc8280xp-edp
29          - qcom,sdm845-dp
30          - qcom,sm8350-dp
31          - qcom,sm8650-dp
32      - items:
33          - enum:
34              - qcom,sm6350-dp
35              - qcom,sm8150-dp
36              - qcom,sm8250-dp
37              - qcom,sm8450-dp
38              - qcom,sm8550-dp
39          - const: qcom,sm8350-dp
40
41  reg:
42    minItems: 4
43    items:
44      - description: ahb register block
45      - description: aux register block
46      - description: link register block
47      - description: p0 register block
48      - description: p1 register block
49
50  interrupts:
51    maxItems: 1
52
53  clocks:
54    items:
55      - description: AHB clock to enable register access
56      - description: Display Port AUX clock
57      - description: Display Port Link clock
58      - description: Link interface clock between DP and PHY
59      - description: Display Port Pixel clock
60
61  clock-names:
62    items:
63      - const: core_iface
64      - const: core_aux
65      - const: ctrl_link
66      - const: ctrl_link_iface
67      - const: stream_pixel
68
69  assigned-clocks:
70    items:
71      - description: link clock source
72      - description: pixel clock source
73
74  assigned-clock-parents:
75    items:
76      - description: phy 0 parent
77      - description: phy 1 parent
78
79  phys:
80    maxItems: 1
81
82  phy-names:
83    items:
84      - const: dp
85
86  operating-points-v2: true
87
88  opp-table:
89    type: object
90
91  power-domains:
92    maxItems: 1
93
94  aux-bus:
95    $ref: /schemas/display/dp-aux-bus.yaml#
96
97  data-lanes:
98    $ref: /schemas/types.yaml#/definitions/uint32-array
99    deprecated: true
100    minItems: 1
101    maxItems: 4
102    items:
103      maximum: 3
104
105  "#sound-dai-cells":
106    const: 0
107
108  vdda-0p9-supply:
109    deprecated: true
110  vdda-1p2-supply:
111    deprecated: true
112
113  ports:
114    $ref: /schemas/graph.yaml#/properties/ports
115    properties:
116      port@0:
117        $ref: /schemas/graph.yaml#/properties/port
118        description: Input endpoint of the controller
119
120      port@1:
121        $ref: /schemas/graph.yaml#/$defs/port-base
122        unevaluatedProperties: false
123        description: Output endpoint of the controller
124        properties:
125          endpoint:
126            $ref: /schemas/media/video-interfaces.yaml#
127            unevaluatedProperties: false
128            properties:
129              data-lanes:
130                minItems: 1
131                maxItems: 4
132                items:
133                  enum: [ 0, 1, 2, 3 ]
134
135              link-frequencies:
136                minItems: 1
137                maxItems: 4
138                items:
139                  enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
140
141    required:
142      - port@0
143      - port@1
144
145required:
146  - compatible
147  - reg
148  - interrupts
149  - clocks
150  - clock-names
151  - phys
152  - phy-names
153  - power-domains
154  - ports
155
156allOf:
157  # AUX BUS does not exist on DP controllers
158  # Audio output also is present only on DP output
159  # p1 regions is present on DP, but not on eDP
160  - if:
161      properties:
162        compatible:
163          contains:
164            enum:
165              - qcom,sc7280-edp
166              - qcom,sc8180x-edp
167              - qcom,sc8280xp-edp
168    then:
169      properties:
170        "#sound-dai-cells": false
171    else:
172      properties:
173        aux-bus: false
174        reg:
175          minItems: 5
176      required:
177        - "#sound-dai-cells"
178
179additionalProperties: false
180
181examples:
182  - |
183    #include <dt-bindings/interrupt-controller/arm-gic.h>
184    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
185    #include <dt-bindings/power/qcom-rpmpd.h>
186
187    displayport-controller@ae90000 {
188        compatible = "qcom,sc7180-dp";
189        reg = <0xae90000 0x200>,
190              <0xae90200 0x200>,
191              <0xae90400 0xc00>,
192              <0xae91000 0x400>,
193              <0xae91400 0x400>;
194        interrupt-parent = <&mdss>;
195        interrupts = <12>;
196        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
197                 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
198                 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
199                 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
200                 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
201        clock-names = "core_iface", "core_aux",
202                      "ctrl_link",
203                      "ctrl_link_iface", "stream_pixel";
204
205        assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
206                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
207
208        assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
209
210        phys = <&dp_phy>;
211        phy-names = "dp";
212
213        #sound-dai-cells = <0>;
214
215        power-domains = <&rpmhpd SC7180_CX>;
216
217        ports {
218            #address-cells = <1>;
219            #size-cells = <0>;
220
221            port@0 {
222                reg = <0>;
223                endpoint {
224                    remote-endpoint = <&dpu_intf0_out>;
225                };
226            };
227
228            port@1 {
229                reg = <1>;
230                endpoint {
231                    remote-endpoint = <&typec>;
232                    data-lanes = <0 1>;
233                    link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
234                };
235            };
236        };
237    };
238...
239