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Searched +full:s32g2 +full:- +full:dwmac (Results 1 – 3 of 3) sorted by relevance

/linux-6.14.4/Documentation/devicetree/bindings/net/
Dnxp,s32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright 2021-2024 NXP
4 ---
5 $id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jan Petrous (OSS) <[email protected]>
15 The SoC series S32G2xx and S32G3xx feature one DWMAC instance,
23 - const: nxp,s32g2-dwmac
24 - items:
25 - enum:
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Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <[email protected]>
11 - Giuseppe Cavallaro <[email protected]>
12 - Jose Abreu <[email protected]>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
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/linux-6.14.4/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-s32.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2019-2024 NXP
10 #include <linux/clk-provider.h>
43 writel(PHY_INTF_SEL_RGMII, gmac->ctrl_sts); in s32_gmac_write_phy_intf_select()
45 dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode)); in s32_gmac_write_phy_intf_select()
56 ret = clk_prepare_enable(gmac->tx_clk); in s32_gmac_init()
58 dev_err(&pdev->dev, "Can't enable tx clock\n"); in s32_gmac_init()
61 ret = clk_set_rate(gmac->tx_clk, GMAC_INTF_RATE_125M); in s32_gmac_init()
63 dev_err(&pdev->dev, "Can't set tx clock\n"); in s32_gmac_init()
68 ret = clk_prepare_enable(gmac->rx_clk); in s32_gmac_init()
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