1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright 2021-2024 NXP
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: NXP S32G2xx/S32G3xx/S32R45 GMAC ethernet controller
9
10maintainers:
11  - Jan Petrous (OSS) <[email protected]>
12
13description:
14  This device is a Synopsys DWC IP, integrated on NXP S32G/R SoCs.
15  The SoC series S32G2xx and S32G3xx feature one DWMAC instance,
16  the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII
17  interface over Pinctrl device or the output can be routed
18  to the embedded SerDes for SGMII connectivity.
19
20properties:
21  compatible:
22    oneOf:
23      - const: nxp,s32g2-dwmac
24      - items:
25          - enum:
26              - nxp,s32g3-dwmac
27              - nxp,s32r45-dwmac
28          - const: nxp,s32g2-dwmac
29
30  reg:
31    items:
32      - description: Main GMAC registers
33      - description: GMAC PHY mode control register
34
35  interrupts:
36    maxItems: 1
37
38  interrupt-names:
39    const: macirq
40
41  clocks:
42    items:
43      - description: Main GMAC clock
44      - description: Transmit clock
45      - description: Receive clock
46      - description: PTP reference clock
47
48  clock-names:
49    items:
50      - const: stmmaceth
51      - const: tx
52      - const: rx
53      - const: ptp_ref
54
55required:
56  - clocks
57  - clock-names
58
59allOf:
60  - $ref: snps,dwmac.yaml#
61
62unevaluatedProperties: false
63
64examples:
65  - |
66    #include <dt-bindings/interrupt-controller/arm-gic.h>
67    #include <dt-bindings/interrupt-controller/irq.h>
68    #include <dt-bindings/phy/phy.h>
69    bus {
70      #address-cells = <2>;
71      #size-cells = <2>;
72
73      ethernet@4033c000 {
74        compatible = "nxp,s32g2-dwmac";
75        reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
76              <0x0 0x4007c004 0x0 0x4>;    /* GMAC_0_CTRL_STS */
77        interrupt-parent = <&gic>;
78        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
79        interrupt-names = "macirq";
80        snps,mtl-rx-config = <&mtl_rx_setup>;
81        snps,mtl-tx-config = <&mtl_tx_setup>;
82        clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>;
83        clock-names = "stmmaceth", "tx", "rx", "ptp_ref";
84        phy-mode = "rgmii-id";
85        phy-handle = <&phy0>;
86
87        mtl_rx_setup: rx-queues-config {
88          snps,rx-queues-to-use = <5>;
89        };
90
91        mtl_tx_setup: tx-queues-config {
92          snps,tx-queues-to-use = <5>;
93        };
94
95        mdio {
96          #address-cells = <1>;
97          #size-cells = <0>;
98          compatible = "snps,dwmac-mdio";
99
100          phy0: ethernet-phy@0 {
101            reg = <0>;
102          };
103        };
104      };
105    };
106