1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright 2019-2024 NXP
10 #include <linux/clk-provider.h>
43 	writel(PHY_INTF_SEL_RGMII, gmac->ctrl_sts);  in s32_gmac_write_phy_intf_select()
45 	dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode));  in s32_gmac_write_phy_intf_select()
56 	ret = clk_prepare_enable(gmac->tx_clk);  in s32_gmac_init()
58 		dev_err(&pdev->dev, "Can't enable tx clock\n");  in s32_gmac_init()
61 	ret = clk_set_rate(gmac->tx_clk, GMAC_INTF_RATE_125M);  in s32_gmac_init()
63 		dev_err(&pdev->dev, "Can't set tx clock\n");  in s32_gmac_init()
68 	ret = clk_prepare_enable(gmac->rx_clk);  in s32_gmac_init()
70 		dev_err(&pdev->dev, "Can't enable rx clock\n");  in s32_gmac_init()
73 	ret = clk_set_rate(gmac->rx_clk, GMAC_INTF_RATE_125M);  in s32_gmac_init()
75 		dev_err(&pdev->dev, "Can't set rx clock\n");  in s32_gmac_init()
82 		dev_err(&pdev->dev, "Can't set PHY interface mode\n");  in s32_gmac_init()
89 	clk_disable_unprepare(gmac->rx_clk);  in s32_gmac_init()
91 	clk_disable_unprepare(gmac->tx_clk);  in s32_gmac_init()
99 	clk_disable_unprepare(gmac->tx_clk);  in s32_gmac_exit()
100 	clk_disable_unprepare(gmac->rx_clk);  in s32_gmac_exit()
111 		dev_err(gmac->dev, "Unsupported/Invalid speed: %d\n", speed);  in s32_fix_mac_speed()
115 	dev_dbg(gmac->dev, "Set tx clock to %ld Hz\n", tx_clk_rate);  in s32_fix_mac_speed()
116 	ret = clk_set_rate(gmac->tx_clk, tx_clk_rate);  in s32_fix_mac_speed()
118 		dev_err(gmac->dev, "Can't set tx clock\n");  in s32_fix_mac_speed()
124 	struct device *dev = &pdev->dev;  in s32_dwmac_probe()
129 	gmac = devm_kzalloc(&pdev->dev, sizeof(*gmac), GFP_KERNEL);  in s32_dwmac_probe()
131 		return -ENOMEM;  in s32_dwmac_probe()
133 	gmac->dev = &pdev->dev;  in s32_dwmac_probe()
146 	gmac->ctrl_sts = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);  in s32_dwmac_probe()
147 	if (IS_ERR(gmac->ctrl_sts))  in s32_dwmac_probe()
148 		return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts),  in s32_dwmac_probe()
152 	gmac->tx_clk = devm_clk_get(&pdev->dev, "tx");  in s32_dwmac_probe()
153 	if (IS_ERR(gmac->tx_clk))  in s32_dwmac_probe()
154 		return dev_err_probe(dev, PTR_ERR(gmac->tx_clk),  in s32_dwmac_probe()
158 	gmac->rx_clk = devm_clk_get(&pdev->dev, "rx");  in s32_dwmac_probe()
159 	if (IS_ERR(gmac->rx_clk))  in s32_dwmac_probe()
160 		return dev_err_probe(dev, PTR_ERR(gmac->rx_clk),  in s32_dwmac_probe()
163 	gmac->intf_mode = &plat->phy_interface;  in s32_dwmac_probe()
164 	gmac->ioaddr = res.addr;  in s32_dwmac_probe()
167 	plat->has_gmac4 = true;  in s32_dwmac_probe()
168 	plat->pmt = 1;  in s32_dwmac_probe()
169 	plat->flags |= STMMAC_FLAG_SPH_DISABLE;  in s32_dwmac_probe()
170 	plat->rx_fifo_size = 20480;  in s32_dwmac_probe()
171 	plat->tx_fifo_size = 20480;  in s32_dwmac_probe()
173 	plat->init = s32_gmac_init;  in s32_dwmac_probe()
174 	plat->exit = s32_gmac_exit;  in s32_dwmac_probe()
175 	plat->fix_mac_speed = s32_fix_mac_speed;  in s32_dwmac_probe()
177 	plat->bsp_priv = gmac;  in s32_dwmac_probe()
183 	{ .compatible = "nxp,s32g2-dwmac" },
192 		.name = "s32-dwmac",