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/linux-6.14.4/Documentation/devicetree/bindings/net/
Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <[email protected]>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
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Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <[email protected]>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
18 connect to a MAC through a standard MII, RMII, or RGMII interface
24 - $ref: ethernet-phy.yaml#
30 ti,link-loss-low:
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Dmediatek,star-emac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek STAR Ethernet MAC Controller
10 - Bartosz Golaszewski <[email protected]>
13 This Ethernet MAC is used on the MT8* family of SoCs from MediaTek.
14 It's compliant with 802.3 standards and supports half- and full-duplex
15 modes with flow-control as well as CRC offloading and VLAN tags.
18 - $ref: ethernet-controller.yaml#
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Dnxp,dwmac-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clark Wang <[email protected]>
11 - Shawn Guo <[email protected]>
12 - NXP Linux Team <linux-[email protected]>
20 - nxp,imx8mp-dwmac-eqos
21 - nxp,imx8dxl-dwmac-eqos
22 - nxp,imx93-dwmac-eqos
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Dsti-dwmac.txt10 - compatible : "st,stih407-dwmac"
11 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
13 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
15 - pinctrl-0: pin-control for all the MII mode supported.
18 - resets : phandle pointing to the system reset controller with correct
20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
21 MAC can generate it.
22 - st,tx-retime-src: This specifies which clk is wired up to the mac for
24 possible values from "txclk", "clk_125" or "clkgen".
26 - sti-ethclk: this is the phy clock.
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/linux-6.14.4/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
79 struct clk *rmii_internal_clk;
103 /* list of clocks required for mac */
114 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
115 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
119 switch (plat->phy_mode) { in mt2712_set_interface()
133 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
134 return -EINVAL; in mt2712_set_interface()
137 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val); in mt2712_set_interface()
144 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_ps2stage()
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Ddwmac-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
9 #include <linux/clk.h>
37 *------------------------------------------
39 *------------------------------------------
41 *------------------------------------------
43 *------------------------------------------
45 *------------------------------------------
46 * RMII | 1 | 0 | 0 | n/a |
47 *------------------------------------------
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Ddwmac-sti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sti.c - STMicroelectronics DWMAC Specific Glue layer
5 * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
18 #include <linux/clk.h>
40 * ------------------------------------------------
43 * ------------------------------------------------
45 *| | clk-125/txclk | txclk |
46 * ------------------------------------------------
48 *| | clk-125/txclk | clkgen |
50 * ------------------------------------------------
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Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
50 /* Bypass (= 0, the signal from the GPIO input directly connects to the
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
94 struct clk *rgmii_tx_clk;
97 struct clk *timing_adj_clk;
112 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
116 writel(data, dwmac->regs + reg); in meson8b_dwmac_mask_bits()
119 static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac, in meson8b_dwmac_register_clk()
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Ddwmac-rk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
5 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
12 #include <linux/clk.h>
72 struct clk *clk_mac;
73 struct clk *clk_phy;
104 struct device *dev = &bsp_priv->pdev->dev; in px30_set_to_rmii()
106 if (IS_ERR(bsp_priv->grf)) { in px30_set_to_rmii()
111 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1, in px30_set_to_rmii()
[all …]
Ddwmac-sun8i.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
8 #include <linux/clk.h>
11 #include <linux/mdio-mux.h>
28 /* General notes on dwmac-sun8i:
33 /* struct emac_variant - Describe dwmac-sun8i hardware variant
39 * @soc_has_internal_phy: Does the MAC embed an internal PHY
40 * @support_mii: Does the MAC handle MII
41 * @support_rmii: Does the MAC handle RMII
42 * @support_rgmii: Does the MAC handle RGMII
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/linux-6.14.4/drivers/clk/
Dclk-aspeed.c1 // SPDX-License-Identifier: GPL-2.0+
4 #define pr_fmt(fmt) "clk-aspeed: " fmt
13 #include <dt-bindings/clock/aspeed-clock.h>
15 #include "clk-aspeed.h"
48 /* clk rst name parent flags */
49 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
50 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
51 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
52 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
53 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
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/linux-6.14.4/drivers/net/ethernet/socionext/
Dsni_ave.c1 // SPDX-License-Identifier: GPL-2.0
3 * sni_ave.c - Socionext UniPhier AVE ethernet driver
5 * Copyright 2015-2017 Socionext Inc.
9 #include <linux/clk.h>
38 /* MAC Register Group */
41 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */
42 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */
84 /* RMII Bridge Register Group */
93 #define AVE_GRR_GRST BIT(0) /* Reset all MAC */
98 #define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */
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/linux-6.14.4/drivers/net/ethernet/actions/
Dowl-emac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Actions Semi Owl SoCs Ethernet MAC driver
10 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
19 #include "owl-emac.h"
27 return readl(priv->base + reg); in owl_emac_reg_read()
32 writel(data, priv->base + reg); in owl_emac_reg_write()
63 return priv->netdev->dev.parent; in owl_emac_get_dev()
84 * unexpected side effect (MAC hardware bug?!) where some bits in the in owl_emac_irq_disable()
129 return dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); in owl_emac_dma_map_tx()
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/linux-6.14.4/drivers/net/ethernet/faraday/
Dftgmac100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
11 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
54 /* For NC-SI to register a fixed-link phy device */
100 struct clk *clk; member
102 /* AST2500/AST2600 RMII ref clock gate */
103 struct clk *rclk;
126 struct net_device *netdev = priv->netdev; in ftgmac100_reset_mac()
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/linux-6.14.4/drivers/net/ethernet/nxp/
Dlpc_eth.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/clk.h>
23 #include <linux/soc/nxp/lpc32xx-misc.h>
25 #define MODNAME "lpc-eth"
35 * Ethernet MAC controller Register offsets
317 if (dev && dev->of_node) { in lpc_phy_interface_mode()
318 const char *mode = of_get_property(dev->of_node, in lpc_phy_interface_mode()
319 "phy-mode", NULL); in lpc_phy_interface_mode()
328 if (dev && dev->of_node) in use_iram_for_net()
329 return of_property_read_bool(dev->of_node, "use-iram"); in use_iram_for_net()
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/linux-6.14.4/arch/arm/boot/dts/nxp/lpc/
Dlpc3250-phy3250.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PHYTEC phyCORE-LPC3250 board
5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <[email protected]>
9 /dts-v1/;
13 model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
22 compatible = "gpio-leds";
26 default-state = "off";
31 linux,default-trigger = "heartbeat";
37 power-supply = <&reg_lcd>;
41 remote-endpoint = <&cldc_output>;
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Dlpc3250-ea3250.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
20 gpio-keys {
21 compatible = "gpio-keys";
86 compatible = "gpio-leds";
92 linux,default-trigger = "timer";
93 default-state = "off";
98 default-state = "off";
103 default-state = "off";
108 default-state = "off";
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/linux-6.14.4/Documentation/networking/device_drivers/ethernet/stmicro/
Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
27 Currently, this network device driver is for all STi embedded MAC/GMAC
32 DesignWare(R) Cores Ethernet MAC 10/100/1000 Universal version 3.70a
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/linux-6.14.4/arch/sh/boards/mach-se/7724/
Dsetup.c1 // SPDX-License-Identifier: GPL-2.0
35 #include <linux/dma-map-ops.h>
37 #include <mach-se/mach/se7724.h>
38 #include <media/drv-intf/renesas-ceu.h>
51 * ------------------------------------
55 * SW41 : abxx xxxx -> a = 0 : Analog monitor
65 * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz,
73 * Please change J20, J21, J22 pin to 1-2 connection.
85 .id = -1,
123 .mask_flags = MTD_WRITEABLE, /* Read-only */
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/linux-6.14.4/drivers/net/dsa/sja1105/
Dsja1105_clocking.c1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2016-2018 NXP
3 * Copyright (c) 2018-2019, Vladimir Oltean <[email protected]>
107 sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op); in sja1105_cgu_idiv_packing()
108 sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op); in sja1105_cgu_idiv_packing()
109 sja1105_packing(buf, &idiv->idiv, 5, 2, size, op); in sja1105_cgu_idiv_packing()
110 sja1105_packing(buf, &idiv->pd, 0, 0, size, op); in sja1105_cgu_idiv_packing()
116 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_idiv_config()
117 struct device *dev = priv->ds->dev; in sja1105_cgu_idiv_config()
121 if (regs->cgu_idiv[port] == SJA1105_RSV_ADDR) in sja1105_cgu_idiv_config()
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/linux-6.14.4/drivers/net/ethernet/ti/
Ddavinci_emac.c1 // SPDX-License-Identifier: GPL-2.0+
9 * ---------------------------------------------------------------------------
11 * 0-5 A number of folks worked on this driver in bits and pieces but the major
12 * contribution came from Suraj Iyer and Anant Gole
13 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
14 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
38 #include <linux/dma-mapping.h>
39 #include <linux/clk.h>
117 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
320 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
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/linux-6.14.4/arch/sh/boards/mach-ecovec24/
Dsetup.c1 // SPDX-License-Identifier: GPL-2.0
39 #include <linux/dma-map-ops.h>
41 #include <media/drv-intf/renesas-ceu.h>
52 *-----------------------------------------
62 *------------------------------
65 * DS2[2] = RMII / TS, SCIF ON : RMII
71 * DS2[6-7] = MMC / SD ON-OFF : SD
72 * OFF-ON : MMC
76 * FSI - DA7210
99 .end = 0xA405012E - 1,
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/linux-6.14.4/drivers/net/phy/
Ddp83td510.c1 // SPDX-License-Identifier: GPL-2.0
16 /* Bit 7 - mii_interrupt, active high. Clears on read.
18 * This differs from the DP83TD510E datasheet (2020) which states this bit
40 * 32-bit or 16-bit counters for TX and RX statistics and must be read in
43 * - DP83TD510E_PKT_STAT_1: Contains TX packet count bits [15:0].
44 * - DP83TD510E_PKT_STAT_2: Contains TX packet count bits [31:16].
45 * - DP83TD510E_PKT_STAT_3: Contains TX error packet count.
46 * - DP83TD510E_PKT_STAT_4: Contains RX packet count bits [15:0].
47 * - DP83TD510E_PKT_STAT_5: Contains RX packet count bits [31:16].
48 * - DP83TD510E_PKT_STAT_6: Contains RX error packet count.
[all …]
/linux-6.14.4/drivers/net/ethernet/cadence/
Dmacb_main.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2006 Atmel Corporation
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
25 #include <linux/dma-mapping.h>
40 #include <linux/firmware/xlnx-zynqmp.h>
58 * (bp)->rx_ring_size)
64 * (bp)->tx_ring_size)
67 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
78 …MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN -…
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