1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83TD510 PHY
3 * Copyright (c) 2022 Pengutronix, Oleksij Rempel <[email protected]>
4 */
5
6 #include <linux/bitfield.h>
7 #include <linux/ethtool_netlink.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/phy.h>
11
12 #define DP83TD510E_PHY_ID 0x20000181
13
14 /* MDIO_MMD_VEND2 registers */
15 #define DP83TD510E_PHY_STS 0x10
16 /* Bit 7 - mii_interrupt, active high. Clears on read.
17 * Note: Clearing does not necessarily deactivate IRQ pin if interrupts pending.
18 * This differs from the DP83TD510E datasheet (2020) which states this bit
19 * clears on write 0.
20 */
21 #define DP83TD510E_STS_MII_INT BIT(7)
22 #define DP83TD510E_LINK_STATUS BIT(0)
23
24 #define DP83TD510E_GEN_CFG 0x11
25 #define DP83TD510E_GENCFG_INT_POLARITY BIT(3)
26 #define DP83TD510E_GENCFG_INT_EN BIT(1)
27 #define DP83TD510E_GENCFG_INT_OE BIT(0)
28
29 #define DP83TD510E_INTERRUPT_REG_1 0x12
30 #define DP83TD510E_INT1_LINK BIT(13)
31 #define DP83TD510E_INT1_LINK_EN BIT(5)
32
33 #define DP83TD510E_CTRL 0x1f
34 #define DP83TD510E_CTRL_HW_RESET BIT(15)
35 #define DP83TD510E_CTRL_SW_RESET BIT(14)
36
37 /*
38 * DP83TD510E_PKT_STAT_x registers correspond to similarly named registers
39 * in the datasheet (PKT_STAT_1 through PKT_STAT_6). These registers store
40 * 32-bit or 16-bit counters for TX and RX statistics and must be read in
41 * sequence to ensure the counters are cleared correctly.
42 *
43 * - DP83TD510E_PKT_STAT_1: Contains TX packet count bits [15:0].
44 * - DP83TD510E_PKT_STAT_2: Contains TX packet count bits [31:16].
45 * - DP83TD510E_PKT_STAT_3: Contains TX error packet count.
46 * - DP83TD510E_PKT_STAT_4: Contains RX packet count bits [15:0].
47 * - DP83TD510E_PKT_STAT_5: Contains RX packet count bits [31:16].
48 * - DP83TD510E_PKT_STAT_6: Contains RX error packet count.
49 *
50 * Keeping the register names as defined in the datasheet helps maintain
51 * clarity and alignment with the documentation.
52 */
53 #define DP83TD510E_PKT_STAT_1 0x12b
54 #define DP83TD510E_PKT_STAT_2 0x12c
55 #define DP83TD510E_PKT_STAT_3 0x12d
56 #define DP83TD510E_PKT_STAT_4 0x12e
57 #define DP83TD510E_PKT_STAT_5 0x12f
58 #define DP83TD510E_PKT_STAT_6 0x130
59
60 #define DP83TD510E_AN_STAT_1 0x60c
61 #define DP83TD510E_MASTER_SLAVE_RESOL_FAIL BIT(15)
62
63 #define DP83TD510E_MSE_DETECT 0xa85
64
65 #define DP83TD510_SQI_MAX 7
66
67 /* Register values are converted to SNR(dB) as suggested by
68 * "Application Report - DP83TD510E Cable Diagnostics Toolkit":
69 * SNR(dB) = -10 * log10 (VAL/2^17) - 1.76 dB.
70 * SQI ranges are implemented according to "OPEN ALLIANCE - Advanced diagnostic
71 * features for 100BASE-T1 automotive Ethernet PHYs"
72 */
73 static const u16 dp83td510_mse_sqi_map[] = {
74 0x0569, /* < 18dB */
75 0x044c, /* 18dB =< SNR < 19dB */
76 0x0369, /* 19dB =< SNR < 20dB */
77 0x02b6, /* 20dB =< SNR < 21dB */
78 0x0227, /* 21dB =< SNR < 22dB */
79 0x01b6, /* 22dB =< SNR < 23dB */
80 0x015b, /* 23dB =< SNR < 24dB */
81 0x0000 /* 24dB =< SNR */
82 };
83
84 struct dp83td510_stats {
85 u64 tx_pkt_cnt;
86 u64 tx_err_pkt_cnt;
87 u64 rx_pkt_cnt;
88 u64 rx_err_pkt_cnt;
89 };
90
91 struct dp83td510_priv {
92 bool alcd_test_active;
93 struct dp83td510_stats stats;
94 };
95
96 /* Time Domain Reflectometry (TDR) Functionality of DP83TD510 PHY
97 *
98 * I assume that this PHY is using a variation of Spread Spectrum Time Domain
99 * Reflectometry (SSTDR) rather than the commonly used TDR found in many PHYs.
100 * Here are the following observations which likely confirm this:
101 * - The DP83TD510 PHY transmits a modulated signal of configurable length
102 * (default 16000 µs) instead of a single pulse pattern, which is typical
103 * for traditional TDR.
104 * - The pulse observed on the wire, triggered by the HW RESET register, is not
105 * part of the cable testing process.
106 *
107 * I assume that SSTDR seems to be a logical choice for the 10BaseT1L
108 * environment due to improved noise resistance, making it suitable for
109 * environments with significant electrical noise, such as long 10BaseT1L cable
110 * runs.
111 *
112 * Configuration Variables:
113 * The SSTDR variation used in this PHY involves more configuration variables
114 * that can dramatically affect the functionality and precision of cable
115 * testing. Since most of these configuration options are either not well
116 * documented or documented with minimal details, the following sections
117 * describe my understanding and observations of these variables and their
118 * impact on TDR functionality.
119 *
120 * Timeline:
121 * ,<--cfg_pre_silence_time
122 * | ,<-SSTDR Modulated Transmission
123 * | | ,<--cfg_post_silence_time
124 * | | | ,<--Force Link Mode
125 * |<--'-->|<-------'------->|<--'-->|<--------'------->|
126 *
127 * - cfg_pre_silence_time: Optional silence time before TDR transmission starts.
128 * - SSTDR Modulated Transmission: Transmission duration configured by
129 * cfg_tdr_tx_duration and amplitude configured by cfg_tdr_tx_type.
130 * - cfg_post_silence_time: Silence time after TDR transmission.
131 * - Force Link Mode: If nothing is configured after cfg_post_silence_time,
132 * the PHY continues in force link mode without autonegotiation.
133 */
134
135 #define DP83TD510E_TDR_CFG 0x1e
136 #define DP83TD510E_TDR_START BIT(15)
137 #define DP83TD510E_TDR_DONE BIT(1)
138 #define DP83TD510E_TDR_FAIL BIT(0)
139
140 #define DP83TD510E_TDR_CFG1 0x300
141 /* cfg_tdr_tx_type: Transmit voltage level for TDR.
142 * 0 = 1V, 1 = 2.4V
143 * Note: Using different voltage levels may not work
144 * in all configuration variations. For example, setting
145 * 2.4V may give different cable length measurements.
146 * Other settings may be needed to make it work properly.
147 */
148 #define DP83TD510E_TDR_TX_TYPE BIT(12)
149 #define DP83TD510E_TDR_TX_TYPE_1V 0
150 #define DP83TD510E_TDR_TX_TYPE_2_4V 1
151 /* cfg_post_silence_time: Time after the TDR sequence. Since we force master mode
152 * for the TDR will proceed with forced link state after this time. For Linux
153 * it is better to set max value to avoid false link state detection.
154 */
155 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME GENMASK(3, 2)
156 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_0MS 0
157 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_10MS 1
158 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_100MS 2
159 #define DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_1000MS 3
160 /* cfg_pre_silence_time: Time before the TDR sequence. It should be enough to
161 * settle down all pulses and reflections. Since for 10BASE-T1L we have
162 * maximum 2000m cable length, we can set it to 1ms.
163 */
164 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME GENMASK(1, 0)
165 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_0MS 0
166 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_10MS 1
167 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_100MS 2
168 #define DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_1000MS 3
169
170 #define DP83TD510E_TDR_CFG2 0x301
171 #define DP83TD510E_TDR_END_TAP_INDEX_1 GENMASK(14, 8)
172 #define DP83TD510E_TDR_END_TAP_INDEX_1_DEF 36
173 #define DP83TD510E_TDR_START_TAP_INDEX_1 GENMASK(6, 0)
174 #define DP83TD510E_TDR_START_TAP_INDEX_1_DEF 4
175
176 #define DP83TD510E_TDR_CFG3 0x302
177 /* cfg_tdr_tx_duration: Duration of the TDR transmission in microseconds.
178 * This value sets the duration of the modulated signal used for TDR
179 * measurements.
180 * - Default: 16000 µs
181 * - Observation: A minimum duration of 6000 µs is recommended to ensure
182 * accurate detection of cable faults. Durations shorter than 6000 µs may
183 * result in incomplete data, especially for shorter cables (e.g., 20 meters),
184 * leading to false "OK" results. Longer durations (e.g., 6000 µs or more)
185 * provide better accuracy, particularly for detecting open circuits.
186 */
187 #define DP83TD510E_TDR_TX_DURATION_US GENMASK(15, 0)
188 #define DP83TD510E_TDR_TX_DURATION_US_DEF 16000
189
190 #define DP83TD510E_TDR_FAULT_CFG1 0x303
191 #define DP83TD510E_TDR_FLT_LOC_OFFSET_1 GENMASK(14, 8)
192 #define DP83TD510E_TDR_FLT_LOC_OFFSET_1_DEF 4
193 #define DP83TD510E_TDR_FLT_INIT_1 GENMASK(7, 0)
194 #define DP83TD510E_TDR_FLT_INIT_1_DEF 62
195
196 #define DP83TD510E_TDR_FAULT_STAT 0x30c
197 #define DP83TD510E_TDR_PEAK_DETECT BIT(11)
198 #define DP83TD510E_TDR_PEAK_SIGN BIT(10)
199 #define DP83TD510E_TDR_PEAK_LOCATION GENMASK(9, 0)
200
201 /* Not documented registers and values but recommended according to
202 * "DP83TD510E Cable Diagnostics Toolkit revC"
203 */
204 #define DP83TD510E_UNKN_030E 0x30e
205 #define DP83TD510E_030E_VAL 0x2520
206
207 #define DP83TD510E_ALCD_STAT 0xa9f
208 #define DP83TD510E_ALCD_COMPLETE BIT(15)
209 #define DP83TD510E_ALCD_CABLE_LENGTH GENMASK(10, 0)
210
211 /**
212 * dp83td510_update_stats - Update the PHY statistics for the DP83TD510 PHY.
213 * @phydev: Pointer to the phy_device structure.
214 *
215 * The function reads the PHY statistics registers and updates the statistics
216 * structure.
217 *
218 * Returns: 0 on success or a negative error code on failure.
219 */
dp83td510_update_stats(struct phy_device * phydev)220 static int dp83td510_update_stats(struct phy_device *phydev)
221 {
222 struct dp83td510_priv *priv = phydev->priv;
223 u32 count;
224 int ret;
225
226 /* The DP83TD510E_PKT_STAT registers are divided into two groups:
227 * - Group 1 (TX stats): DP83TD510E_PKT_STAT_1 to DP83TD510E_PKT_STAT_3
228 * - Group 2 (RX stats): DP83TD510E_PKT_STAT_4 to DP83TD510E_PKT_STAT_6
229 *
230 * Registers in each group are cleared only after reading them in a
231 * plain sequence (e.g., 1, 2, 3 for Group 1 or 4, 5, 6 for Group 2).
232 * Any deviation from the sequence, such as reading 1, 2, 1, 2, 3, will
233 * prevent the group from being cleared. Additionally, the counters
234 * for a group are frozen as soon as the first register in that group
235 * is accessed.
236 */
237 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_1);
238 if (ret < 0)
239 return ret;
240 /* tx_pkt_cnt_15_0 */
241 count = ret;
242
243 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_2);
244 if (ret < 0)
245 return ret;
246 /* tx_pkt_cnt_31_16 */
247 count |= ret << 16;
248 priv->stats.tx_pkt_cnt += count;
249
250 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_3);
251 if (ret < 0)
252 return ret;
253 /* tx_err_pkt_cnt */
254 priv->stats.tx_err_pkt_cnt += ret;
255
256 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_4);
257 if (ret < 0)
258 return ret;
259 /* rx_pkt_cnt_15_0 */
260 count = ret;
261
262 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_5);
263 if (ret < 0)
264 return ret;
265 /* rx_pkt_cnt_31_16 */
266 count |= ret << 16;
267 priv->stats.rx_pkt_cnt += count;
268
269 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PKT_STAT_6);
270 if (ret < 0)
271 return ret;
272 /* rx_err_pkt_cnt */
273 priv->stats.rx_err_pkt_cnt += ret;
274
275 return 0;
276 }
277
dp83td510_get_phy_stats(struct phy_device * phydev,struct ethtool_eth_phy_stats * eth_stats,struct ethtool_phy_stats * stats)278 static void dp83td510_get_phy_stats(struct phy_device *phydev,
279 struct ethtool_eth_phy_stats *eth_stats,
280 struct ethtool_phy_stats *stats)
281 {
282 struct dp83td510_priv *priv = phydev->priv;
283
284 stats->tx_packets = priv->stats.tx_pkt_cnt;
285 stats->tx_errors = priv->stats.tx_err_pkt_cnt;
286 stats->rx_packets = priv->stats.rx_pkt_cnt;
287 stats->rx_errors = priv->stats.rx_err_pkt_cnt;
288 }
289
dp83td510_config_intr(struct phy_device * phydev)290 static int dp83td510_config_intr(struct phy_device *phydev)
291 {
292 int ret;
293
294 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
295 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
296 DP83TD510E_INTERRUPT_REG_1,
297 DP83TD510E_INT1_LINK_EN);
298 if (ret)
299 return ret;
300
301 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
302 DP83TD510E_GEN_CFG,
303 DP83TD510E_GENCFG_INT_POLARITY |
304 DP83TD510E_GENCFG_INT_EN |
305 DP83TD510E_GENCFG_INT_OE);
306 } else {
307 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
308 DP83TD510E_INTERRUPT_REG_1, 0x0);
309 if (ret)
310 return ret;
311
312 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2,
313 DP83TD510E_GEN_CFG,
314 DP83TD510E_GENCFG_INT_EN);
315 if (ret)
316 return ret;
317 }
318
319 return ret;
320 }
321
dp83td510_handle_interrupt(struct phy_device * phydev)322 static irqreturn_t dp83td510_handle_interrupt(struct phy_device *phydev)
323 {
324 int ret;
325
326 /* Read the current enabled interrupts */
327 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_INTERRUPT_REG_1);
328 if (ret < 0) {
329 phy_error(phydev);
330 return IRQ_NONE;
331 } else if (!(ret & DP83TD510E_INT1_LINK_EN) ||
332 !(ret & DP83TD510E_INT1_LINK)) {
333 return IRQ_NONE;
334 }
335
336 phy_trigger_machine(phydev);
337
338 return IRQ_HANDLED;
339 }
340
dp83td510_read_status(struct phy_device * phydev)341 static int dp83td510_read_status(struct phy_device *phydev)
342 {
343 u16 phy_sts;
344 int ret;
345
346 phydev->speed = SPEED_UNKNOWN;
347 phydev->duplex = DUPLEX_UNKNOWN;
348 phydev->pause = 0;
349 phydev->asym_pause = 0;
350 linkmode_zero(phydev->lp_advertising);
351
352 phy_sts = phy_read(phydev, DP83TD510E_PHY_STS);
353
354 phydev->link = !!(phy_sts & DP83TD510E_LINK_STATUS);
355 if (phydev->link) {
356 /* This PHY supports only one link mode: 10BaseT1L_Full */
357 phydev->duplex = DUPLEX_FULL;
358 phydev->speed = SPEED_10;
359
360 if (phydev->autoneg == AUTONEG_ENABLE) {
361 ret = genphy_c45_read_lpa(phydev);
362 if (ret)
363 return ret;
364
365 phy_resolve_aneg_linkmode(phydev);
366 }
367 }
368
369 if (phydev->autoneg == AUTONEG_ENABLE) {
370 ret = genphy_c45_baset1_read_status(phydev);
371 if (ret < 0)
372 return ret;
373
374 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
375 DP83TD510E_AN_STAT_1);
376 if (ret < 0)
377 return ret;
378
379 if (ret & DP83TD510E_MASTER_SLAVE_RESOL_FAIL)
380 phydev->master_slave_state = MASTER_SLAVE_STATE_ERR;
381 } else {
382 return genphy_c45_pma_baset1_read_master_slave(phydev);
383 }
384
385 return 0;
386 }
387
dp83td510_config_aneg(struct phy_device * phydev)388 static int dp83td510_config_aneg(struct phy_device *phydev)
389 {
390 bool changed = false;
391 int ret;
392
393 ret = genphy_c45_pma_baset1_setup_master_slave(phydev);
394 if (ret < 0)
395 return ret;
396
397 if (phydev->autoneg == AUTONEG_DISABLE)
398 return genphy_c45_an_disable_aneg(phydev);
399
400 ret = genphy_c45_an_config_aneg(phydev);
401 if (ret < 0)
402 return ret;
403 if (ret > 0)
404 changed = true;
405
406 return genphy_c45_check_and_restart_aneg(phydev, changed);
407 }
408
dp83td510_get_sqi(struct phy_device * phydev)409 static int dp83td510_get_sqi(struct phy_device *phydev)
410 {
411 int sqi, ret;
412 u16 mse_val;
413
414 if (!phydev->link)
415 return 0;
416
417 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_MSE_DETECT);
418 if (ret < 0)
419 return ret;
420
421 mse_val = 0xFFFF & ret;
422 for (sqi = 0; sqi < ARRAY_SIZE(dp83td510_mse_sqi_map); sqi++) {
423 if (mse_val >= dp83td510_mse_sqi_map[sqi])
424 return sqi;
425 }
426
427 return -EINVAL;
428 }
429
dp83td510_get_sqi_max(struct phy_device * phydev)430 static int dp83td510_get_sqi_max(struct phy_device *phydev)
431 {
432 return DP83TD510_SQI_MAX;
433 }
434
435 /**
436 * dp83td510_cable_test_start - Start the cable test for the DP83TD510 PHY.
437 * @phydev: Pointer to the phy_device structure.
438 *
439 * This sequence is implemented according to the "Application Note DP83TD510E
440 * Cable Diagnostics Toolkit revC".
441 *
442 * Returns: 0 on success, a negative error code on failure.
443 */
dp83td510_cable_test_start(struct phy_device * phydev)444 static int dp83td510_cable_test_start(struct phy_device *phydev)
445 {
446 struct dp83td510_priv *priv = phydev->priv;
447 int ret;
448
449 /* If link partner is active, we won't be able to use TDR, since
450 * we can't force link partner to be silent. The autonegotiation
451 * pulses will be too frequent and the TDR sequence will be
452 * too long. So, TDR will always fail. Since the link is established
453 * we already know that the cable is working, so we can get some
454 * extra information line the cable length using ALCD.
455 */
456 if (phydev->link) {
457 priv->alcd_test_active = true;
458 return 0;
459 }
460
461 priv->alcd_test_active = false;
462
463 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL,
464 DP83TD510E_CTRL_HW_RESET);
465 if (ret)
466 return ret;
467
468 ret = genphy_c45_an_disable_aneg(phydev);
469 if (ret)
470 return ret;
471
472 /* Force master mode */
473 ret = phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
474 MDIO_PMA_PMD_BT1_CTRL_CFG_MST);
475 if (ret)
476 return ret;
477
478 /* There is no official recommendation for this register, but it is
479 * better to use 1V for TDR since other values seems to be optimized
480 * for this amplitude. Except of amplitude, it is better to configure
481 * pre TDR silence time to 10ms to avoid false reflections (value 0
482 * seems to be too short, otherwise we need to implement own silence
483 * time). Also, post TDR silence time should be set to 1000ms to avoid
484 * false link state detection, it fits to the polling time of the
485 * PHY framework. The idea is to wait until
486 * dp83td510_cable_test_get_status() will be called and reconfigure
487 * the PHY to the default state within the post silence time window.
488 */
489 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG1,
490 DP83TD510E_TDR_TX_TYPE |
491 DP83TD510E_TDR_CFG1_POST_SILENCE_TIME |
492 DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME,
493 DP83TD510E_TDR_TX_TYPE_1V |
494 DP83TD510E_TDR_CFG1_PRE_SILENCE_TIME_10MS |
495 DP83TD510E_TDR_CFG1_POST_SILENCE_TIME_1000MS);
496 if (ret)
497 return ret;
498
499 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG2,
500 FIELD_PREP(DP83TD510E_TDR_END_TAP_INDEX_1,
501 DP83TD510E_TDR_END_TAP_INDEX_1_DEF) |
502 FIELD_PREP(DP83TD510E_TDR_START_TAP_INDEX_1,
503 DP83TD510E_TDR_START_TAP_INDEX_1_DEF));
504 if (ret)
505 return ret;
506
507 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_FAULT_CFG1,
508 FIELD_PREP(DP83TD510E_TDR_FLT_LOC_OFFSET_1,
509 DP83TD510E_TDR_FLT_LOC_OFFSET_1_DEF) |
510 FIELD_PREP(DP83TD510E_TDR_FLT_INIT_1,
511 DP83TD510E_TDR_FLT_INIT_1_DEF));
512 if (ret)
513 return ret;
514
515 /* Undocumented register, from the "Application Note DP83TD510E Cable
516 * Diagnostics Toolkit revC".
517 */
518 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_UNKN_030E,
519 DP83TD510E_030E_VAL);
520 if (ret)
521 return ret;
522
523 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG3,
524 DP83TD510E_TDR_TX_DURATION_US_DEF);
525 if (ret)
526 return ret;
527
528 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_CTRL,
529 DP83TD510E_CTRL_SW_RESET);
530 if (ret)
531 return ret;
532
533 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG,
534 DP83TD510E_TDR_START);
535 }
536
537 /**
538 * dp83td510_cable_test_get_tdr_status - Get the status of the TDR test for the
539 * DP83TD510 PHY.
540 * @phydev: Pointer to the phy_device structure.
541 * @finished: Pointer to a boolean that indicates whether the test is finished.
542 *
543 * The function sets the @finished flag to true if the test is complete.
544 *
545 * Returns: 0 on success or a negative error code on failure.
546 */
dp83td510_cable_test_get_tdr_status(struct phy_device * phydev,bool * finished)547 static int dp83td510_cable_test_get_tdr_status(struct phy_device *phydev,
548 bool *finished)
549 {
550 int ret, stat;
551
552 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_TDR_CFG);
553 if (ret < 0)
554 return ret;
555
556 if (!(ret & DP83TD510E_TDR_DONE))
557 return 0;
558
559 if (!(ret & DP83TD510E_TDR_FAIL)) {
560 int location;
561
562 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
563 DP83TD510E_TDR_FAULT_STAT);
564 if (ret < 0)
565 return ret;
566
567 if (ret & DP83TD510E_TDR_PEAK_DETECT) {
568 if (ret & DP83TD510E_TDR_PEAK_SIGN)
569 stat = ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
570 else
571 stat = ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
572
573 location = FIELD_GET(DP83TD510E_TDR_PEAK_LOCATION,
574 ret) * 100;
575 ethnl_cable_test_fault_length(phydev,
576 ETHTOOL_A_CABLE_PAIR_A,
577 location);
578 } else {
579 stat = ETHTOOL_A_CABLE_RESULT_CODE_OK;
580 }
581 } else {
582 /* Most probably we have active link partner */
583 stat = ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
584 }
585
586 *finished = true;
587
588 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, stat);
589
590 return phy_init_hw(phydev);
591 }
592
593 /**
594 * dp83td510_cable_test_get_alcd_status - Get the status of the ALCD test for the
595 * DP83TD510 PHY.
596 * @phydev: Pointer to the phy_device structure.
597 * @finished: Pointer to a boolean that indicates whether the test is finished.
598 *
599 * The function sets the @finished flag to true if the test is complete.
600 * The function reads the cable length and reports it to the user.
601 *
602 * Returns: 0 on success or a negative error code on failure.
603 */
dp83td510_cable_test_get_alcd_status(struct phy_device * phydev,bool * finished)604 static int dp83td510_cable_test_get_alcd_status(struct phy_device *phydev,
605 bool *finished)
606 {
607 unsigned int location;
608 int ret, phy_sts;
609
610 phy_sts = phy_read(phydev, DP83TD510E_PHY_STS);
611
612 if (!(phy_sts & DP83TD510E_LINK_STATUS)) {
613 /* If the link is down, we can't do any thing usable now */
614 ethnl_cable_test_result_with_src(phydev, ETHTOOL_A_CABLE_PAIR_A,
615 ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC,
616 ETHTOOL_A_CABLE_INF_SRC_ALCD);
617 *finished = true;
618 return 0;
619 }
620
621 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_ALCD_STAT);
622 if (ret < 0)
623 return ret;
624
625 if (!(ret & DP83TD510E_ALCD_COMPLETE))
626 return 0;
627
628 location = FIELD_GET(DP83TD510E_ALCD_CABLE_LENGTH, ret) * 100;
629
630 ethnl_cable_test_fault_length_with_src(phydev, ETHTOOL_A_CABLE_PAIR_A,
631 location,
632 ETHTOOL_A_CABLE_INF_SRC_ALCD);
633
634 ethnl_cable_test_result_with_src(phydev, ETHTOOL_A_CABLE_PAIR_A,
635 ETHTOOL_A_CABLE_RESULT_CODE_OK,
636 ETHTOOL_A_CABLE_INF_SRC_ALCD);
637 *finished = true;
638
639 return 0;
640 }
641
642 /**
643 * dp83td510_cable_test_get_status - Get the status of the cable test for the
644 * DP83TD510 PHY.
645 * @phydev: Pointer to the phy_device structure.
646 * @finished: Pointer to a boolean that indicates whether the test is finished.
647 *
648 * The function sets the @finished flag to true if the test is complete.
649 *
650 * Returns: 0 on success or a negative error code on failure.
651 */
dp83td510_cable_test_get_status(struct phy_device * phydev,bool * finished)652 static int dp83td510_cable_test_get_status(struct phy_device *phydev,
653 bool *finished)
654 {
655 struct dp83td510_priv *priv = phydev->priv;
656 *finished = false;
657
658 if (priv->alcd_test_active)
659 return dp83td510_cable_test_get_alcd_status(phydev, finished);
660
661 return dp83td510_cable_test_get_tdr_status(phydev, finished);
662 }
663
dp83td510_get_features(struct phy_device * phydev)664 static int dp83td510_get_features(struct phy_device *phydev)
665 {
666 /* This PHY can't respond on MDIO bus if no RMII clock is enabled.
667 * In case RMII mode is used (most meaningful mode for this PHY) and
668 * the PHY do not have own XTAL, and CLK providing MAC is not probed,
669 * we won't be able to read all needed ability registers.
670 * So provide it manually.
671 */
672
673 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
674 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
675 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
676 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
677 phydev->supported);
678
679 return 0;
680 }
681
dp83td510_probe(struct phy_device * phydev)682 static int dp83td510_probe(struct phy_device *phydev)
683 {
684 struct device *dev = &phydev->mdio.dev;
685 struct dp83td510_priv *priv;
686
687 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
688 if (!priv)
689 return -ENOMEM;
690
691 phydev->priv = priv;
692
693 return 0;
694 }
695
696 static struct phy_driver dp83td510_driver[] = {
697 {
698 PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID),
699 .name = "TI DP83TD510E",
700
701 .flags = PHY_POLL_CABLE_TEST,
702 .probe = dp83td510_probe,
703 .config_aneg = dp83td510_config_aneg,
704 .read_status = dp83td510_read_status,
705 .get_features = dp83td510_get_features,
706 .config_intr = dp83td510_config_intr,
707 .handle_interrupt = dp83td510_handle_interrupt,
708 .get_sqi = dp83td510_get_sqi,
709 .get_sqi_max = dp83td510_get_sqi_max,
710 .cable_test_start = dp83td510_cable_test_start,
711 .cable_test_get_status = dp83td510_cable_test_get_status,
712 .get_phy_stats = dp83td510_get_phy_stats,
713 .update_stats = dp83td510_update_stats,
714
715 .suspend = genphy_suspend,
716 .resume = genphy_resume,
717 } };
718 module_phy_driver(dp83td510_driver);
719
720 static const struct mdio_device_id __maybe_unused dp83td510_tbl[] = {
721 { PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID) },
722 { }
723 };
724 MODULE_DEVICE_TABLE(mdio, dp83td510_tbl);
725
726 MODULE_DESCRIPTION("Texas Instruments DP83TD510E PHY driver");
727 MODULE_AUTHOR("Oleksij Rempel <[email protected]>");
728 MODULE_LICENSE("GPL v2");
729