1 // SPDX-License-Identifier: GPL-2.0
16 /* Bit 7 - mii_interrupt, active high. Clears on read.
18  * This differs from the DP83TD510E datasheet (2020) which states this bit
40  * 32-bit or 16-bit counters for TX and RX statistics and must be read in
43  * - DP83TD510E_PKT_STAT_1: Contains TX packet count bits [15:0].
44  * - DP83TD510E_PKT_STAT_2: Contains TX packet count bits [31:16].
45  * - DP83TD510E_PKT_STAT_3: Contains TX error packet count.
46  * - DP83TD510E_PKT_STAT_4: Contains RX packet count bits [15:0].
47  * - DP83TD510E_PKT_STAT_5: Contains RX packet count bits [31:16].
48  * - DP83TD510E_PKT_STAT_6: Contains RX error packet count.
68  * "Application Report - DP83TD510E Cable Diagnostics Toolkit":
69  * SNR(dB) = -10 * log10 (VAL/2^17) - 1.76 dB.
70  * SQI ranges are implemented according to "OPEN ALLIANCE - Advanced diagnostic
71  * features for 100BASE-T1 automotive Ethernet PHYs"
101  * - The DP83TD510 PHY transmits a modulated signal of configurable length
104  * - The pulse observed on the wire, triggered by the HW RESET register, is not
121  *     ,<--cfg_pre_silence_time
122  *     |            ,<-SSTDR Modulated Transmission
123  *     |	    |            ,<--cfg_post_silence_time
124  *     |	    |            |             ,<--Force Link Mode
125  * |<--'-->|<-------'------->|<--'-->|<--------'------->|
127  * - cfg_pre_silence_time: Optional silence time before TDR transmission starts.
128  * - SSTDR Modulated Transmission: Transmission duration configured by
130  * - cfg_post_silence_time: Silence time after TDR transmission.
131  * - Force Link Mode: If nothing is configured after cfg_post_silence_time,
161  * settle down all pulses and reflections. Since for 10BASE-T1L we have
180  * - Default: 16000 µs
181  * - Observation: A minimum duration of 6000 µs is recommended to ensure
212  * dp83td510_update_stats - Update the PHY statistics for the DP83TD510 PHY.
222 	struct dp83td510_priv *priv = phydev->priv;  in dp83td510_update_stats()
227 	 * - Group 1 (TX stats): DP83TD510E_PKT_STAT_1 to DP83TD510E_PKT_STAT_3  in dp83td510_update_stats()
228 	 * - Group 2 (RX stats): DP83TD510E_PKT_STAT_4 to DP83TD510E_PKT_STAT_6  in dp83td510_update_stats()
232 	 * Any deviation from the sequence, such as reading 1, 2, 1, 2, 3, will  in dp83td510_update_stats()
233 	 * prevent the group from being cleared. Additionally, the counters  in dp83td510_update_stats()
248 	priv->stats.tx_pkt_cnt += count;  in dp83td510_update_stats()
254 	priv->stats.tx_err_pkt_cnt += ret;  in dp83td510_update_stats()
267 	priv->stats.rx_pkt_cnt += count;  in dp83td510_update_stats()
273 	priv->stats.rx_err_pkt_cnt += ret;  in dp83td510_update_stats()
282 	struct dp83td510_priv *priv = phydev->priv;  in dp83td510_get_phy_stats()
284 	stats->tx_packets = priv->stats.tx_pkt_cnt;  in dp83td510_get_phy_stats()
285 	stats->tx_errors = priv->stats.tx_err_pkt_cnt;  in dp83td510_get_phy_stats()
286 	stats->rx_packets = priv->stats.rx_pkt_cnt;  in dp83td510_get_phy_stats()
287 	stats->rx_errors = priv->stats.rx_err_pkt_cnt;  in dp83td510_get_phy_stats()
294 	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {  in dp83td510_config_intr()
346 	phydev->speed = SPEED_UNKNOWN;  in dp83td510_read_status()
347 	phydev->duplex = DUPLEX_UNKNOWN;  in dp83td510_read_status()
348 	phydev->pause = 0;  in dp83td510_read_status()
349 	phydev->asym_pause = 0;  in dp83td510_read_status()
350 	linkmode_zero(phydev->lp_advertising);  in dp83td510_read_status()
354 	phydev->link = !!(phy_sts & DP83TD510E_LINK_STATUS);  in dp83td510_read_status()
355 	if (phydev->link) {  in dp83td510_read_status()
357 		phydev->duplex = DUPLEX_FULL;  in dp83td510_read_status()
358 		phydev->speed = SPEED_10;  in dp83td510_read_status()
360 		if (phydev->autoneg == AUTONEG_ENABLE) {  in dp83td510_read_status()
369 	if (phydev->autoneg == AUTONEG_ENABLE) {  in dp83td510_read_status()
380 			phydev->master_slave_state = MASTER_SLAVE_STATE_ERR;  in dp83td510_read_status()
397 	if (phydev->autoneg == AUTONEG_DISABLE)  in dp83td510_config_aneg()
414 	if (!phydev->link)  in dp83td510_get_sqi()
427 	return -EINVAL;  in dp83td510_get_sqi()
436  * dp83td510_cable_test_start - Start the cable test for the DP83TD510 PHY.
446 	struct dp83td510_priv *priv = phydev->priv;  in dp83td510_cable_test_start()
456 	if (phydev->link) {  in dp83td510_cable_test_start()
457 		priv->alcd_test_active = true;  in dp83td510_cable_test_start()
461 	priv->alcd_test_active = false;  in dp83td510_cable_test_start()
515 	/* Undocumented register, from the "Application Note DP83TD510E Cable  in dp83td510_cable_test_start()
538  * dp83td510_cable_test_get_tdr_status - Get the status of the TDR test for the
594  * dp83td510_cable_test_get_alcd_status - Get the status of the ALCD test for the
643  * dp83td510_cable_test_get_status - Get the status of the cable test for the
655 	struct dp83td510_priv *priv = phydev->priv;  in dp83td510_cable_test_get_status()
658 	if (priv->alcd_test_active)  in dp83td510_cable_test_get_status()
666 	/* This PHY can't respond on MDIO bus if no RMII clock is enabled.  in dp83td510_get_features()
667 	 * In case RMII mode is used (most meaningful mode for this PHY) and  in dp83td510_get_features()
668 	 * the PHY do not have own XTAL, and CLK providing MAC is not probed,  in dp83td510_get_features()
673 	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);  in dp83td510_get_features()
674 	linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);  in dp83td510_get_features()
675 	linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);  in dp83td510_get_features()
677 			 phydev->supported);  in dp83td510_get_features()
684 	struct device *dev = &phydev->mdio.dev;  in dp83td510_probe()
689 		return -ENOMEM;  in dp83td510_probe()
691 	phydev->priv = priv;  in dp83td510_probe()