Home
last modified time | relevance | path

Searched +full:pwr +full:- +full:ctl (Results 1 – 25 of 44) sorted by relevance

12

/linux-6.14.4/drivers/media/pci/ttpci/
Dbudget.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Copyright (C) 1999-2002 Ralph Metzler
48 struct saa7146_dev *dev = budget->dev; in Set22K()
62 struct saa7146_dev *dev = budget->dev; in DiseqcSendBit()
78 for (i = 7; i >= 0; i--) { in DiseqcSendByte()
89 struct saa7146_dev *dev = budget->dev; in SendDiSEqCMsg()
102 if (burst != -1) { in SendDiSEqCMsg()
126 struct saa7146_dev *dev = budget->dev; in SetVoltage_Activy()
143 return -EINVAL; in SetVoltage_Activy()
152 struct budget *budget = fe->dvb->priv; in siemens_budget_set_voltage()
[all …]
/linux-6.14.4/sound/soc/codecs/
Dcs35l32.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * cs35l32.h -- CS35L32 ALSA SoC audio driver
36 #define CS35L32_PWRCTL1 0x06 /* Power Ctl 1 */
37 #define CS35L32_PWRCTL2 0x07 /* Power Ctl 2 */
38 #define CS35L32_CLK_CTL 0x08 /* Clock Ctl */
41 #define CS35L32_BST_CPCP_CTL 0x0B /* Conv Peak Curr Protection CTL */
43 #define CS35L32_AUDIO_LED_MNGR 0x0D /* Audio/LED Pwr Manager */
45 #define CS35L32_CLASSD_CTL 0x10 /* Class D Amp CTL */
46 #define CS35L32_PROTECT_CTL 0x11 /* Protection Release CTL */
Dcs35l32.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cs35l32.c -- CS35L32 ALSA SoC audio driver
26 #include <sound/soc-dapm.h>
29 #include <dt-bindings/sound/cs35l32.h>
50 { 0x06, 0x04 }, /* Power Ctl 1 */
51 { 0x07, 0xE8 }, /* Power Ctl 2 */
52 { 0x08, 0x40 }, /* Clock Ctl */
55 { 0x0B, 0x40 }, /* Conv Peak Curr Protection CTL */
57 { 0x0D, 0x03 }, /* Audio/LED Pwr Manager */
59 { 0x10, 0x14 }, /* Class D Amp CTL */
[all …]
Dcs42l56.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cs42l56.c -- CS42L56 ALSA SoC audio driver
29 #include <sound/soc-dapm.h>
63 { 3, 0x7f }, /* r03 - Power Ctl 1 */
64 { 4, 0xff }, /* r04 - Power Ctl 2 */
65 { 5, 0x00 }, /* ro5 - Clocking Ctl 1 */
66 { 6, 0x0b }, /* r06 - Clocking Ctl 2 */
67 { 7, 0x00 }, /* r07 - Serial Format */
68 { 8, 0x05 }, /* r08 - Class H Ctl */
69 { 9, 0x0c }, /* r09 - Misc Ctl */
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/pci/
Dnvidia,tegra194-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
12 - Vidya Sagar <[email protected]>
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
23 Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
29 - nvidia,tegra194-pcie-ep
[all …]
Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
12 - Vidya Sagar <[email protected]>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
[all …]
/linux-6.14.4/sound/pci/ctxfi/
Dcthw20k1.c1 // SPDX-License-Identifier: GPL-2.0-only
76 * Fixed-point value in 8.24 format for parameter channel */
82 u16 ctl:1; member
88 u16 czbfs:1; /* Clear Z-Buffers */
95 unsigned int ctl; member
162 return -ENOMEM; in src_get_rsc_ctrl_blk()
178 struct src_rsc_ctrl_blk *ctl = blk; in src_set_state() local
180 set_field(&ctl->ctl, SRCCTL_STATE, state); in src_set_state()
181 ctl->dirty.bf.ctl = 1; in src_set_state()
187 struct src_rsc_ctrl_blk *ctl = blk; in src_set_bm() local
[all …]
/linux-6.14.4/arch/arm/boot/dts/rockchip/
Drk3288-rock2-square.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "rk3288-rock2-som.dtsi"
9 compatible = "radxa,rock2-square", "rockchip,rk3288";
12 stdout-path = "serial2:115200n8";
15 adc-keys {
16 compatible = "adc-keys";
17 io-channels = <&saradc 1>;
18 io-channel-names = "buttons";
[all …]
Drk3188-radxarock.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
23 gpio-keys {
24 compatible = "gpio-keys";
27 key-power {
31 linux,input-type = <1>;
32 wakeup-source;
33 debounce-interval = <100>;
37 gpio-leds {
[all …]
Drk3188-bqedison2qc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/i2c/i2c.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 model = "BQ Edison2 Quad-Core";
15 compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188";
29 compatible = "pwm-backlight";
30 power-supply = <&vsys>;
34 gpio-keys {
[all …]
Drk3036-kylin.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
9 compatible = "rockchip,rk3036-kylin", "rockchip,rk3036";
12 stdout-path = "serial2:115200n8";
20 hdmi_con: hdmi-con {
21 compatible = "hdmi-connector";
26 remote-endpoint = <&hdmi_out_con>;
31 leds: gpio-leds {
32 compatible = "gpio-leds";
34 work_led: led-0 {
[all …]
/linux-6.14.4/arch/arm64/boot/dts/nvidia/
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
[all …]
Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
[all …]
/linux-6.14.4/drivers/media/i2c/
Dtvp7002_reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
6 * Author: Santiago Nunez-Corrales <[email protected]>
15 * ------------------
19 * CTL: Control
30 * PWR: Power
/linux-6.14.4/drivers/pcmcia/
Dtcic.c3 Device driver for Databook TCIC-2 PCMCIA controller
55 MODULE_DESCRIPTION("Databook TCIC-2 PCMCIA socket driver");
62 /* The base port address of the TCIC-2 chip */
66 static int ignore = -1;
76 /* The card status change interrupt -- 0 means autoselect */
79 /* Poll status interval -- 0 means default to interrupt */
82 /* Delay for card status double-checking */
195 return 2*(ns-14)/cycle_time; in to_cycles()
214 return -1; in try_irq()
218 return -1; in try_irq()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
[all …]
/linux-6.14.4/arch/arm/boot/dts/nvidia/
Dtegra30-cardhu.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/thermal/thermal.h>
5 #include "tegra30-cpu-opp.dtsi"
6 #include "tegra30-cpu-opp-microvolt.dtsi"
16 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
17 * tegra30-cardhu-a04.dts.
20 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
22 * The (downstream internal) U-Boot of Cardhu display the board-id as
43 stdout-path = "serial0:115200n8";
[all …]
Dtegra30-apalis-v1.1.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
16 avdd-pexa-supply = <&vdd2_reg>;
17 avdd-pexb-supply = <&vdd2_reg>;
18 avdd-pex-pll-supply = <&vdd2_reg>;
19 avdd-plle-supply = <&ldo6_reg>;
20 hvdd-pex-supply = <&reg_module_3v3>;
21 vddio-pex-ctl-supply = <&reg_module_3v3>;
22 vdd-pexa-supply = <&vdd2_reg>;
23 vdd-pexb-supply = <&vdd2_reg>;
27 nvidia,num-lanes = <4>;
[all …]
Dtegra30-apalis.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 avdd-pexa-supply = <&vdd2_reg>;
16 avdd-pexb-supply = <&vdd2_reg>;
17 avdd-pex-pll-supply = <&vdd2_reg>;
18 avdd-plle-supply = <&ldo6_reg>;
19 hvdd-pex-supply = <&reg_module_3v3>;
20 vddio-pex-ctl-supply = <&reg_module_3v3>;
21 vdd-pexa-supply = <&vdd2_reg>;
22 vdd-pexb-supply = <&vdd2_reg>;
26 nvidia,num-lanes = <4>;
[all …]
/linux-6.14.4/drivers/net/wireless/intel/iwlegacy/
D3945.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32 #define IL3945_FW_PRE "iwlwifi-3945-"
41 * Use default noise value of -127 ... this is below the range of measurable
43 * Also, -127 works better than 0 when averaging frames with/without
47 #define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
49 /* Module parameters accessible from iwl-*.c */
146 #define IL_INVALID_VALUE -1
160 container_of(&x->u.rx_frame.stats, \
[all …]
/linux-6.14.4/drivers/video/fbdev/matrox/
Dmatroxfb_DAC1064.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * (c) 1998-2002 Petr Vandrovec <[email protected]>
51 p = (1 << p) - 1; in DAC1064_calcclock()
94 DAC1064_calcclock(minfo, fout, minfo->max_pixel_clock, &m, &n, &p); in DAC1064_setpclk()
95 minfo->hw.DACclk[0] = m; in DAC1064_setpclk()
96 minfo->hw.DACclk[1] = n; in DAC1064_setpclk()
97 minfo->hw.DACclk[2] = p; in DAC1064_setpclk()
104 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_setmclk()
108 if (minfo->devflags.noinit) { in DAC1064_setmclk()
110 hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM); in DAC1064_setmclk()
[all …]
/linux-6.14.4/arch/arm64/boot/dts/rockchip/
Drk3368-orion-r68-meta.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
12 compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
21 stdout-path = "serial2:115200n8";
29 emmc_pwrseq: emmc-pwrseq {
30 compatible = "mmc-pwrseq-emmc";
31 pinctrl-0 = <&emmc_reset>;
32 pinctrl-names = "default";
33 reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
[all …]
Drk3368-r88.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
21 stdout-path = "serial2:115200n8";
29 emmc_pwrseq: emmc-pwrseq {
30 compatible = "mmc-pwrseq-emmc";
31 pinctrl-0 = <&emmc_reset>;
32 pinctrl-names = "default";
33 reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
36 keys: gpio-keys {
[all …]
/linux-6.14.4/drivers/net/wireless/ath/ath9k/
Dar9003_eeprom.c2 * Copyright (c) 2010-2011 Atheros Communications Inc.
30 /* Local defines to distinguish between extension and control CTL's */
36 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
37 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
39 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6)) macro
67 * bit0 - enable tx temp comp - disabled
68 * bit1 - enable tx volt comp - disabled
69 * bit2 - enable fastClock - enabled
70 * bit3 - enable doubling - enabled
71 * bit4 - enable internal regulator - disabled
[all …]
/linux-6.14.4/drivers/net/wireless/ath/ath5k/
Dphy.c2 * Copyright (c) 2004-2007 Reyk Floeter <[email protected]>
3 * Copyright (c) 2006-2009 Nick Kossifidis <[email protected]>
4 * Copyright (c) 2007-2008 Jiri Slaby <[email protected]>
5 * Copyright (c) 2008-2009 Felix Fietkau <[email protected]>
42 * Here we handle the low-level functions related to baseband
48 * - Channel setting/switching
50 * - Automatic Gain Control (AGC) calibration
52 * - Noise Floor calibration
54 * - I/Q imbalance calibration (QAM correction)
56 * - Calibration due to thermal changes (gain_F)
[all …]

12