Lines Matching +full:pwr +full:- +full:ctl
1 // SPDX-License-Identifier: GPL-2.0-only
6 * (c) 1998-2002 Petr Vandrovec <[email protected]>
51 p = (1 << p) - 1; in DAC1064_calcclock()
94 DAC1064_calcclock(minfo, fout, minfo->max_pixel_clock, &m, &n, &p); in DAC1064_setpclk()
95 minfo->hw.DACclk[0] = m; in DAC1064_setpclk()
96 minfo->hw.DACclk[1] = n; in DAC1064_setpclk()
97 minfo->hw.DACclk[2] = p; in DAC1064_setpclk()
104 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_setmclk()
108 if (minfo->devflags.noinit) { in DAC1064_setmclk()
110 hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM); in DAC1064_setmclk()
111 hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN); in DAC1064_setmclk()
112 hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP); in DAC1064_setmclk()
115 mx = hw->MXoptionReg | 0x00000004; in DAC1064_setmclk()
116 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); in DAC1064_setmclk()
131 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); in DAC1064_setmclk()
133 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); in DAC1064_setmclk()
136 Doing so cause immediate PCI lockup :-( Maybe they should in DAC1064_setmclk()
142 DAC1064_calcclock(minfo, fmem, minfo->max_pixel_clock, &m, &n, &p); in DAC1064_setmclk()
143 outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3] = m); in DAC1064_setmclk()
144 outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4] = n); in DAC1064_setmclk()
145 outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5] = p); in DAC1064_setmclk()
146 for (clk = 65536; clk; --clk) { in DAC1064_setmclk()
158 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); in DAC1064_setmclk()
160 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, mx); in DAC1064_setmclk()
161 hw->MXoptionReg = mx; in DAC1064_setmclk()
169 struct matrox_hw_state *hw = &minfo->hw; in g450_set_plls()
173 c2_ctl = hw->crtc2.ctl & ~0x4007; /* Clear PLL + enable for CRTC2 */ in g450_set_plls()
175 hw->DACreg[POS1064_XPWRCTRL] &= ~0x02; /* Stop VIDEO PLL */ in g450_set_plls()
176 pixelmnp = minfo->crtc1.mnp; in g450_set_plls()
177 videomnp = minfo->crtc2.mnp; in g450_set_plls()
180 hw->DACreg[POS1064_XPWRCTRL] &= ~0x10; /* Powerdown CRTC2 */ in g450_set_plls()
181 } else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) { in g450_set_plls()
194 hw->DACreg[POS1064_XPWRCTRL] |= 0x02; in g450_set_plls()
196 outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]); in g450_set_plls()
200 hw->DACreg[POS1064_XPIXCLKCTRL] &= ~M1064_XPIXCLKCTRL_PLL_UP; in g450_set_plls()
202 hw->DACreg[POS1064_XPIXCLKCTRL] |= M1064_XPIXCLKCTRL_PLL_UP; in g450_set_plls()
204 outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]); in g450_set_plls()
207 if (c2_ctl != hw->crtc2.ctl) { in g450_set_plls()
208 hw->crtc2.ctl = c2_ctl; in g450_set_plls()
212 pxc = minfo->crtc1.pixclock; in g450_set_plls()
213 if (pxc == 0 || minfo->outputs[2].src == MATROXFB_SRC_CRTC2) { in g450_set_plls()
214 pxc = minfo->crtc2.pixclock; in g450_set_plls()
216 if (minfo->chip == MGA_G550) { in g450_set_plls()
218 hw->DACreg[POS1064_XPANMODE] = 0x00; /* 0-50 */ in g450_set_plls()
220 hw->DACreg[POS1064_XPANMODE] = 0x08; /* 34-62 */ in g450_set_plls()
222 hw->DACreg[POS1064_XPANMODE] = 0x10; /* 42-78 */ in g450_set_plls()
224 hw->DACreg[POS1064_XPANMODE] = 0x18; /* 62-92 */ in g450_set_plls()
226 hw->DACreg[POS1064_XPANMODE] = 0x20; /* 74-108 */ in g450_set_plls()
228 hw->DACreg[POS1064_XPANMODE] = 0x28; /* 94-122 */ in g450_set_plls()
230 hw->DACreg[POS1064_XPANMODE] = 0x30; /* 108-132 */ in g450_set_plls()
232 hw->DACreg[POS1064_XPANMODE] = 0x38; /* 120-168 */ in g450_set_plls()
237 hw->DACreg[POS1064_XPANMODE] = 0x00; /* 0-54 */ in g450_set_plls()
239 hw->DACreg[POS1064_XPANMODE] = 0x08; /* 38-70 */ in g450_set_plls()
241 hw->DACreg[POS1064_XPANMODE] = 0x10; /* 56-96 */ in g450_set_plls()
243 hw->DACreg[POS1064_XPANMODE] = 0x18; /* 80-114 */ in g450_set_plls()
245 hw->DACreg[POS1064_XPANMODE] = 0x20; /* 102-144 */ in g450_set_plls()
247 hw->DACreg[POS1064_XPANMODE] = 0x28; /* 132-166 */ in g450_set_plls()
249 hw->DACreg[POS1064_XPANMODE] = 0x30; /* 154-182 */ in g450_set_plls()
251 hw->DACreg[POS1064_XPANMODE] = 0x38; /* 170-204 */ in g450_set_plls()
259 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_global_init()
261 hw->DACreg[POS1064_XMISCCTRL] &= M1064_XMISCCTRL_DAC_WIDTHMASK; in DAC1064_global_init()
262 hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_LUT_EN; in DAC1064_global_init()
263 …hw->DACreg[POS1064_XPIXCLKCTRL] = M1064_XPIXCLKCTRL_PLL_UP | M1064_XPIXCLKCTRL_EN | M1064_XPIXCLKC… in DAC1064_global_init()
265 if (minfo->devflags.g450dac) { in DAC1064_global_init()
266 hw->DACreg[POS1064_XPWRCTRL] = 0x1F; /* powerup everything */ in DAC1064_global_init()
267 hw->DACreg[POS1064_XOUTPUTCONN] = 0x00; /* disable outputs */ in DAC1064_global_init()
268 hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_DAC_EN; in DAC1064_global_init()
269 switch (minfo->outputs[0].src) { in DAC1064_global_init()
272 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x01; /* enable output; CRTC1/2 selection is in CRTC2 ctl */ in DAC1064_global_init()
275 hw->DACreg[POS1064_XMISCCTRL] &= ~M1064_XMISCCTRL_DAC_EN; in DAC1064_global_init()
278 switch (minfo->outputs[1].src) { in DAC1064_global_init()
280 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x04; in DAC1064_global_init()
283 if (minfo->outputs[1].mode == MATROXFB_OUTPUT_MODE_MONITOR) { in DAC1064_global_init()
284 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x08; in DAC1064_global_init()
286 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x0C; in DAC1064_global_init()
290 hw->DACreg[POS1064_XPWRCTRL] &= ~0x01; /* Poweroff DAC2 */ in DAC1064_global_init()
293 switch (minfo->outputs[2].src) { in DAC1064_global_init()
295 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x20; in DAC1064_global_init()
298 hw->DACreg[POS1064_XOUTPUTCONN] |= 0x40; in DAC1064_global_init()
307 hw->DACreg[POS1064_XPWRCTRL] &= ~0x04; /* Poweroff TMDS */ in DAC1064_global_init()
316 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1) { in DAC1064_global_init()
317 …hw->DACreg[POS1064_XPIXCLKCTRL] = M1064_XPIXCLKCTRL_PLL_UP | M1064_XPIXCLKCTRL_EN | M1064_XPIXCLKC… in DAC1064_global_init()
318 hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_MAFC | G400_XMISCCTRL_VDO_MAFC12; in DAC1064_global_init()
319 } else if (minfo->outputs[1].src == MATROXFB_SRC_CRTC2) { in DAC1064_global_init()
320 hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_MAFC | G400_XMISCCTRL_VDO_C2_MAFC12; in DAC1064_global_init()
321 } else if (minfo->outputs[2].src == MATROXFB_SRC_CRTC1) in DAC1064_global_init()
322 hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_PANELLINK | G400_XMISCCTRL_VDO_MAFC12; in DAC1064_global_init()
324 hw->DACreg[POS1064_XMISCCTRL] |= GX00_XMISCCTRL_MFC_DIS; in DAC1064_global_init()
326 if (minfo->outputs[0].src != MATROXFB_SRC_NONE) in DAC1064_global_init()
327 hw->DACreg[POS1064_XMISCCTRL] |= M1064_XMISCCTRL_DAC_EN; in DAC1064_global_init()
333 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_global_restore()
335 outDAC1064(minfo, M1064_XPIXCLKCTRL, hw->DACreg[POS1064_XPIXCLKCTRL]); in DAC1064_global_restore()
336 outDAC1064(minfo, M1064_XMISCCTRL, hw->DACreg[POS1064_XMISCCTRL]); in DAC1064_global_restore()
337 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) { in DAC1064_global_restore()
339 outDAC1064(minfo, 0x1F, minfo->devflags.dfp_type); in DAC1064_global_restore()
340 if (minfo->devflags.g450dac) { in DAC1064_global_restore()
342 outDAC1064(minfo, M1064_XPWRCTRL, hw->DACreg[POS1064_XPWRCTRL]); in DAC1064_global_restore()
343 outDAC1064(minfo, M1064_XPANMODE, hw->DACreg[POS1064_XPANMODE]); in DAC1064_global_restore()
344 outDAC1064(minfo, M1064_XOUTPUTCONN, hw->DACreg[POS1064_XOUTPUTCONN]); in DAC1064_global_restore()
351 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_init_1()
355 memcpy(hw->DACreg, MGA1064_DAC, sizeof(MGA1064_DAC_regs)); in DAC1064_init_1()
356 switch (minfo->fbcon.var.bits_per_pixel) { in DAC1064_init_1()
359 hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_8BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED; in DAC1064_init_1()
362 if (minfo->fbcon.var.green.length == 5) in DAC1064_init_1()
363 …hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_15BPP_1BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED; in DAC1064_init_1()
365 hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_16BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED; in DAC1064_init_1()
368 hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_24BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED; in DAC1064_init_1()
371 hw->DACreg[POS1064_XMULCTRL] = M1064_XMULCTRL_DEPTH_32BPP | M1064_XMULCTRL_GRAPHICS_PALETIZED; in DAC1064_init_1()
376 hw->DACreg[POS1064_XVREFCTRL] = minfo->features.DAC1064.xvrefctrl; in DAC1064_init_1()
377 hw->DACreg[POS1064_XGENCTRL] &= ~M1064_XGENCTRL_SYNC_ON_GREEN_MASK; in DAC1064_init_1()
378 …hw->DACreg[POS1064_XGENCTRL] |= (m->sync & FB_SYNC_ON_GREEN)?M1064_XGENCTRL_SYNC_ON_GREEN:M1064_XG… in DAC1064_init_1()
379 hw->DACreg[POS1064_XCURADDL] = 0; in DAC1064_init_1()
380 hw->DACreg[POS1064_XCURADDH] = 0; in DAC1064_init_1()
388 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_init_2()
392 if (minfo->fbcon.var.bits_per_pixel > 16) { /* 256 entries */ in DAC1064_init_2()
396 hw->DACpal[i * 3 + 0] = i; in DAC1064_init_2()
397 hw->DACpal[i * 3 + 1] = i; in DAC1064_init_2()
398 hw->DACpal[i * 3 + 2] = i; in DAC1064_init_2()
400 } else if (minfo->fbcon.var.bits_per_pixel > 8) { in DAC1064_init_2()
401 if (minfo->fbcon.var.green.length == 5) { /* 0..31, 128..159 */ in DAC1064_init_2()
406 hw->DACpal[i * 3 + 0] = i << 3; in DAC1064_init_2()
407 hw->DACpal[i * 3 + 1] = i << 3; in DAC1064_init_2()
408 hw->DACpal[i * 3 + 2] = i << 3; in DAC1064_init_2()
410 hw->DACpal[(i + 128) * 3 + 0] = i << 3; in DAC1064_init_2()
411 hw->DACpal[(i + 128) * 3 + 1] = i << 3; in DAC1064_init_2()
412 hw->DACpal[(i + 128) * 3 + 2] = i << 3; in DAC1064_init_2()
418 hw->DACpal[i * 3 + 0] = i << 3; in DAC1064_init_2()
419 hw->DACpal[i * 3 + 1] = i << 2; in DAC1064_init_2()
420 hw->DACpal[i * 3 + 2] = i << 3; in DAC1064_init_2()
424 memset(hw->DACpal, 0, 768); in DAC1064_init_2()
431 struct matrox_hw_state *hw = &minfo->hw; in DAC1064_restore_1()
439 if ((inDAC1064(minfo, DAC1064_XSYSPLLM) != hw->DACclk[3]) || in DAC1064_restore_1()
440 (inDAC1064(minfo, DAC1064_XSYSPLLN) != hw->DACclk[4]) || in DAC1064_restore_1()
441 (inDAC1064(minfo, DAC1064_XSYSPLLP) != hw->DACclk[5])) { in DAC1064_restore_1()
442 outDAC1064(minfo, DAC1064_XSYSPLLM, hw->DACclk[3]); in DAC1064_restore_1()
443 outDAC1064(minfo, DAC1064_XSYSPLLN, hw->DACclk[4]); in DAC1064_restore_1()
444 outDAC1064(minfo, DAC1064_XSYSPLLP, hw->DACclk[5]); in DAC1064_restore_1()
451 outDAC1064(minfo, MGA1064_DAC_regs[i], hw->DACreg[i]); in DAC1064_restore_1()
471 dprintk("R%02X=%02X ", MGA1064_DAC_regs[i], minfo->hw.DACreg[i]); in DAC1064_restore_2()
476 dprintk("C%02X=%02X ", i, minfo->hw.DACclk[i]); in DAC1064_restore_2()
488 DAC1064_setpclk(minfo, m->pixclock); in m1064_compute()
493 outDAC1064(minfo, M1064_XPIXPLLCM + i, minfo->hw.DACclk[i]); in m1064_compute()
494 for (tmout = 500000; tmout; tmout--) { in m1064_compute()
517 if (m->mnp < 0) { in g450_compute()
518 …m->mnp = matroxfb_g450_setclk(minfo, m->pixclock, (m->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C … in g450_compute()
519 if (m->mnp >= 0) { in g450_compute()
520 m->pixclock = g450_mnp2f(minfo, m->mnp); in g450_compute()
538 struct matrox_hw_state *hw = &minfo->hw; in MGA1064_init()
545 hw->MiscOutReg = 0xCB; in MGA1064_init()
546 if (m->sync & FB_SYNC_HOR_HIGH_ACT) in MGA1064_init()
547 hw->MiscOutReg &= ~0x40; in MGA1064_init()
548 if (m->sync & FB_SYNC_VERT_HIGH_ACT) in MGA1064_init()
549 hw->MiscOutReg &= ~0x80; in MGA1064_init()
550 if (m->sync & FB_SYNC_COMP_HIGH_ACT) /* should be only FB_SYNC_COMP */ in MGA1064_init()
551 hw->CRTCEXT[3] |= 0x40; in MGA1064_init()
561 struct matrox_hw_state *hw = &minfo->hw; in MGAG100_init()
566 hw->MXoptionReg &= ~0x2000; in MGAG100_init()
569 hw->MiscOutReg = 0xEF; in MGAG100_init()
570 if (m->sync & FB_SYNC_HOR_HIGH_ACT) in MGAG100_init()
571 hw->MiscOutReg &= ~0x40; in MGAG100_init()
572 if (m->sync & FB_SYNC_VERT_HIGH_ACT) in MGAG100_init()
573 hw->MiscOutReg &= ~0x80; in MGAG100_init()
574 if (m->sync & FB_SYNC_COMP_HIGH_ACT) /* should be only FB_SYNC_COMP */ in MGAG100_init()
575 hw->CRTCEXT[3] |= 0x40; in MGAG100_init()
588 /* minfo->features.DAC1064.vco_freq_min = 120000; */ in MGA1064_ramdac_init()
589 minfo->features.pll.vco_freq_min = 62000; in MGA1064_ramdac_init()
590 minfo->features.pll.ref_freq = 14318; in MGA1064_ramdac_init()
591 minfo->features.pll.feed_div_min = 100; in MGA1064_ramdac_init()
592 minfo->features.pll.feed_div_max = 127; in MGA1064_ramdac_init()
593 minfo->features.pll.in_div_min = 1; in MGA1064_ramdac_init()
594 minfo->features.pll.in_div_max = 31; in MGA1064_ramdac_init()
595 minfo->features.pll.post_shift_max = 3; in MGA1064_ramdac_init()
596 minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_EXTERNAL; in MGA1064_ramdac_init()
639 for (clk = 500000; clk; clk--) { in MGAG100_progPixClock()
645 …printk(KERN_ERR "matroxfb: Pixel PLL%c not locked after usual time\n", (reg-M1064_XPIXPLLAM-2)/4 +… in MGAG100_progPixClock()
663 DAC1064_calcclock(minfo, freq, minfo->max_pixel_clock, &m, &n, &p); in MGAG100_setPixClock()
674 struct matrox_hw_state *hw = &minfo->hw; in MGA1064_preinit()
678 /* minfo->capable.cfb4 = 0; ... preinitialized by 0 */ in MGA1064_preinit()
679 minfo->capable.text = 1; in MGA1064_preinit()
680 minfo->capable.vxres = vxres_mystique; in MGA1064_preinit()
682 minfo->outputs[0].output = &m1064; in MGA1064_preinit()
683 minfo->outputs[0].src = minfo->outputs[0].default_src; in MGA1064_preinit()
684 minfo->outputs[0].data = minfo; in MGA1064_preinit()
685 minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR; in MGA1064_preinit()
687 if (minfo->devflags.noinit) in MGA1064_preinit()
689 hw->MXoptionReg &= 0xC0000100; in MGA1064_preinit()
690 hw->MXoptionReg |= 0x00094E20; in MGA1064_preinit()
691 if (minfo->devflags.novga) in MGA1064_preinit()
692 hw->MXoptionReg &= ~0x00000100; in MGA1064_preinit()
693 if (minfo->devflags.nobios) in MGA1064_preinit()
694 hw->MXoptionReg &= ~0x40000000; in MGA1064_preinit()
695 if (minfo->devflags.nopciretry) in MGA1064_preinit()
696 hw->MXoptionReg |= 0x20000000; in MGA1064_preinit()
697 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGA1064_preinit()
720 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4); in g450_mclk_init()
721 pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3 & ~0x00300C03); in g450_mclk_init()
722 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_mclk_init()
724 if (((minfo->values.reg.opt3 & 0x000003) == 0x000003) || in g450_mclk_init()
725 ((minfo->values.reg.opt3 & 0x000C00) == 0x000C00) || in g450_mclk_init()
726 ((minfo->values.reg.opt3 & 0x300000) == 0x300000)) { in g450_mclk_init()
727 matroxfb_g450_setclk(minfo, minfo->values.pll.video, M_VIDEO_PLL); in g450_mclk_init()
730 unsigned int pwr; in g450_mclk_init() local
733 pwr = inDAC1064(minfo, M1064_XPWRCTRL) & ~0x02; in g450_mclk_init()
734 outDAC1064(minfo, M1064_XPWRCTRL, pwr); in g450_mclk_init()
737 matroxfb_g450_setclk(minfo, minfo->values.pll.system, M_SYSTEM_PLL); in g450_mclk_init()
740 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg | 4); in g450_mclk_init()
741 pci_write_config_dword(minfo->pcidev, PCI_OPTION3_REG, minfo->values.reg.opt3); in g450_mclk_init()
742 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_mclk_init()
749 minfo->hw.MXoptionReg &= ~0x001F8000; in g450_memory_init()
750 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_memory_init()
753 minfo->hw.MXoptionReg &= ~0x00207E00; in g450_memory_init()
754 minfo->hw.MXoptionReg |= 0x00207E00 & minfo->values.reg.opt; in g450_memory_init()
755 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_memory_init()
756 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, minfo->values.reg.opt2); in g450_memory_init()
758 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); in g450_memory_init()
761 pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc & ~0x80000000U); in g450_memory_init()
762 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); in g450_memory_init()
763 mga_outl(M_MACCESS, minfo->values.reg.maccess); in g450_memory_init()
765 pci_write_config_dword(minfo->pcidev, PCI_MEMMISC_REG, minfo->values.reg.memmisc | 0x80000000U); in g450_memory_init()
769 if (minfo->values.memory.ddr && (!minfo->values.memory.emrswen || !minfo->values.memory.dll)) { in g450_memory_init()
770 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk & ~0x1000); in g450_memory_init()
772 mga_outl(M_MACCESS, minfo->values.reg.maccess | 0x8000); in g450_memory_init()
776 minfo->hw.MXoptionReg |= 0x001F8000 & minfo->values.reg.opt; in g450_memory_init()
777 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_memory_init()
783 if (minfo->values.reg.mctlwtst != minfo->values.reg.mctlwtst_core) { in g450_memory_init()
784 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst_core); in g450_memory_init()
795 /* minfo->hw.MXoptionReg = minfo->values.reg.opt; */ in g450_preinit()
796 minfo->hw.MXoptionReg &= 0xC0000100; in g450_preinit()
797 minfo->hw.MXoptionReg |= 0x00000020; in g450_preinit()
798 if (minfo->devflags.novga) in g450_preinit()
799 minfo->hw.MXoptionReg &= ~0x00000100; in g450_preinit()
800 if (minfo->devflags.nobios) in g450_preinit()
801 minfo->hw.MXoptionReg &= ~0x40000000; in g450_preinit()
802 if (minfo->devflags.nopciretry) in g450_preinit()
803 minfo->hw.MXoptionReg |= 0x20000000; in g450_preinit()
804 minfo->hw.MXoptionReg |= minfo->values.reg.opt & 0x03400040; in g450_preinit()
805 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg); in g450_preinit()
843 struct matrox_hw_state *hw = &minfo->hw; in MGAG100_preinit()
853 if (minfo->devflags.g450dac) { in MGAG100_preinit()
854 minfo->features.pll.vco_freq_min = 130000; /* my sample: >118 */ in MGAG100_preinit()
856 minfo->features.pll.vco_freq_min = 62000; in MGAG100_preinit()
858 if (!minfo->features.pll.ref_freq) { in MGAG100_preinit()
859 minfo->features.pll.ref_freq = 27000; in MGAG100_preinit()
861 minfo->features.pll.feed_div_min = 7; in MGAG100_preinit()
862 minfo->features.pll.feed_div_max = 127; in MGAG100_preinit()
863 minfo->features.pll.in_div_min = 1; in MGAG100_preinit()
864 minfo->features.pll.in_div_max = 31; in MGAG100_preinit()
865 minfo->features.pll.post_shift_max = 3; in MGAG100_preinit()
866 minfo->features.DAC1064.xvrefctrl = DAC1064_XVREFCTRL_G100_DEFAULT; in MGAG100_preinit()
867 /* minfo->capable.cfb4 = 0; ... preinitialized by 0 */ in MGAG100_preinit()
868 minfo->capable.text = 1; in MGAG100_preinit()
869 minfo->capable.vxres = vxres_g100; in MGAG100_preinit()
870 minfo->capable.plnwt = minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100 in MGAG100_preinit()
871 ? minfo->devflags.sgram : 1; in MGAG100_preinit()
873 if (minfo->devflags.g450dac) { in MGAG100_preinit()
874 minfo->outputs[0].output = &g450out; in MGAG100_preinit()
876 minfo->outputs[0].output = &m1064; in MGAG100_preinit()
878 minfo->outputs[0].src = minfo->outputs[0].default_src; in MGAG100_preinit()
879 minfo->outputs[0].data = minfo; in MGAG100_preinit()
880 minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR; in MGAG100_preinit()
882 if (minfo->devflags.g450dac) { in MGAG100_preinit()
887 if (minfo->devflags.noinit) in MGAG100_preinit()
889 if (minfo->devflags.g450dac) { in MGAG100_preinit()
893 hw->MXoptionReg &= 0xC0000100; in MGAG100_preinit()
894 hw->MXoptionReg |= 0x00000020; in MGAG100_preinit()
895 if (minfo->devflags.novga) in MGAG100_preinit()
896 hw->MXoptionReg &= ~0x00000100; in MGAG100_preinit()
897 if (minfo->devflags.nobios) in MGAG100_preinit()
898 hw->MXoptionReg &= ~0x40000000; in MGAG100_preinit()
899 if (minfo->devflags.nopciretry) in MGAG100_preinit()
900 hw->MXoptionReg |= 0x20000000; in MGAG100_preinit()
901 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGAG100_preinit()
904 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG100) { in MGAG100_preinit()
905 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50); in MGAG100_preinit()
907 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50); in MGAG100_preinit()
909 hw->MXoptionReg |= 0x1080; in MGAG100_preinit()
910 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGAG100_preinit()
911 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); in MGAG100_preinit()
921 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50); in MGAG100_preinit()
927 mga_writeb(minfo->video.vbase, 0x0000, 0xAA); in MGAG100_preinit()
928 mga_writeb(minfo->video.vbase, 0x0800, 0x55); in MGAG100_preinit()
929 mga_writeb(minfo->video.vbase, 0x4000, 0x55); in MGAG100_preinit()
931 if (mga_readb(minfo->video.vbase, 0x0000) != 0xAA) { in MGAG100_preinit()
932 hw->MXoptionReg &= ~0x1000; in MGAG100_preinit()
935 hw->MXoptionReg |= 0x00078020; in MGAG100_preinit()
936 } else if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG200) { in MGAG100_preinit()
937 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50); in MGAG100_preinit()
939 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50); in MGAG100_preinit()
941 if (minfo->devflags.memtype == -1) in MGAG100_preinit()
942 hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00; in MGAG100_preinit()
944 hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10; in MGAG100_preinit()
945 if (minfo->devflags.sgram) in MGAG100_preinit()
946 hw->MXoptionReg |= 0x4000; in MGAG100_preinit()
947 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); in MGAG100_preinit()
948 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); in MGAG100_preinit()
953 mga_outw(M_MEMRDBK, minfo->values.reg.memrdbk); in MGAG100_preinit()
954 hw->MXoptionReg |= 0x00078020; in MGAG100_preinit()
956 pci_read_config_dword(minfo->pcidev, PCI_OPTION2_REG, ®50); in MGAG100_preinit()
959 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, reg50); in MGAG100_preinit()
961 if (minfo->devflags.memtype == -1) in MGAG100_preinit()
962 hw->MXoptionReg |= minfo->values.reg.opt & 0x1C00; in MGAG100_preinit()
964 hw->MXoptionReg |= (minfo->devflags.memtype & 7) << 10; in MGAG100_preinit()
965 if (minfo->devflags.sgram) in MGAG100_preinit()
966 hw->MXoptionReg |= 0x4000; in MGAG100_preinit()
967 mga_outl(M_CTLWTST, minfo->values.reg.mctlwtst); in MGAG100_preinit()
968 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); in MGAG100_preinit()
973 mga_outl(M_MEMRDBK, minfo->values.reg.memrdbk); in MGAG100_preinit()
974 hw->MXoptionReg |= 0x00040020; in MGAG100_preinit()
976 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGAG100_preinit()
983 struct matrox_hw_state *hw = &minfo->hw; in MGAG100_reset()
993 if (b == minfo->pcidev->bus->number) { in MGAG100_reset()
994 pci_write_config_byte(ibm, PCI_COMMAND+1, 0); /* disable back-to-back & SERR */ in MGAG100_reset()
1000 if (!minfo->devflags.noinit) { in MGAG100_reset()
1002 hw->MXoptionReg |= 0x40; /* FIXME... */ in MGAG100_reset()
1003 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGAG100_reset()
1008 if (minfo->devflags.g450dac) { in MGAG100_reset()
1010 hw->DACclk[3] = inDAC1064(minfo, DAC1064_XSYSPLLM); in MGAG100_reset()
1011 hw->DACclk[4] = inDAC1064(minfo, DAC1064_XSYSPLLN); in MGAG100_reset()
1012 hw->DACclk[5] = inDAC1064(minfo, DAC1064_XSYSPLLP); in MGAG100_reset()
1016 if (minfo->devflags.accelerator == FB_ACCEL_MATROX_MGAG400) { in MGAG100_reset()
1017 if (minfo->devflags.dfp_type == -1) { in MGAG100_reset()
1018 minfo->devflags.dfp_type = inDAC1064(minfo, 0x1F); in MGAG100_reset()
1021 if (minfo->devflags.noinit) in MGAG100_reset()
1023 if (minfo->devflags.g450dac) { in MGAG100_reset()
1041 struct matrox_hw_state *hw = &minfo->hw; in MGA1064_restore()
1049 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGA1064_restore()
1057 minfo->crtc1.panpos = -1; in MGA1064_restore()
1059 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]); in MGA1064_restore()
1068 struct matrox_hw_state *hw = &minfo->hw; in MGAG100_restore()
1076 pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg); in MGAG100_restore()
1081 if (minfo->devflags.support32MB) in MGAG100_restore()
1082 mga_setr(M_EXTVGA_INDEX, 8, hw->CRTCEXT[8]); in MGAG100_restore()
1083 minfo->crtc1.panpos = -1; in MGAG100_restore()
1085 mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]); in MGAG100_restore()