Lines Matching +full:pwr +full:- +full:ctl
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
30 /* Local defines to distinguish between extension and control CTL's */
36 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
37 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
39 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6)) macro
67 * bit0 - enable tx temp comp - disabled
68 * bit1 - enable tx volt comp - disabled
69 * bit2 - enable fastClock - enabled
70 * bit3 - enable doubling - enabled
71 * bit4 - enable internal regulator - disabled
72 * bit5 - enable pa predistortion - disabled
74 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
119 .noiseFloorThreshCh = {-1, 0, 0},
128 .adcDesiredSize = -30,
177 /* 1L-5L,5S,11L,11S */
182 /* 6-24,36,48,54 */
284 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
285 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
286 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
288 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
289 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
290 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
292 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
293 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
294 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
296 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
297 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
298 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
322 .noiseFloorThreshCh = {-1, 0, 0},
331 .adcDesiredSize = -30,
426 /* 6-24,36,48,54 */
438 * 0_8_16,1-3_9-11_17-19,
452 * 0_8_16,1-3_9-11_17-19,
570 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
571 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
576 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
577 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
582 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
583 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
588 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
589 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
594 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
595 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
600 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
601 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
606 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
607 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
612 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
613 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
618 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
619 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
629 .custData = {"x113-023-f0000"},
645 * bit0 - enable tx temp comp - disabled
646 * bit1 - enable tx volt comp - disabled
647 * bit2 - enable fastClock - enabled
648 * bit3 - enable doubling - enabled
649 * bit4 - enable internal regulator - disabled
650 * bit5 - enable pa predistortion - disabled
652 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
697 .noiseFloorThreshCh = {-1, 0, 0},
706 .adcDesiredSize = -30,
755 /* 1L-5L,5S,11L,11S */
760 /* 6-24,36,48,54 */
862 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
863 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
864 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
866 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
867 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
868 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
870 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
871 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
872 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
874 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
875 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
876 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
900 .noiseFloorThreshCh = {-1, 0, 0},
909 .adcDesiredSize = -30,
1004 /* 6-24,36,48,54 */
1016 * 0_8_16,1-3_9-11_17-19,
1030 * 0_8_16,1-3_9-11_17-19,
1148 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1149 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1154 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1155 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1160 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1161 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1166 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1167 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1172 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1173 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1178 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1179 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1184 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1185 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1190 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1191 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1196 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1197 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1208 .custData = {"h112-241-f0000"},
1224 * bit0 - enable tx temp comp - disabled
1225 * bit1 - enable tx volt comp - disabled
1226 * bit2 - enable fastClock - enabled
1227 * bit3 - enable doubling - enabled
1228 * bit4 - enable internal regulator - disabled
1229 * bit5 - enable pa predistortion - disabled
1231 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1276 .noiseFloorThreshCh = {-1, 0, 0},
1285 .adcDesiredSize = -30,
1334 /* 1L-5L,5S,11L,11S */
1339 /* 6-24,36,48,54 */
1441 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1442 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1443 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1445 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
1446 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1447 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1449 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1450 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1451 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1453 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1454 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1455 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1479 .noiseFloorThreshCh = {-1, 0, 0},
1488 .adcDesiredSize = -30,
1583 /* 6-24,36,48,54 */
1595 * 0_8_16,1-3_9-11_17-19,
1609 * 0_8_16,1-3_9-11_17-19,
1727 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1728 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1733 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1734 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1739 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1740 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1745 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1746 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1751 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1752 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1757 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1758 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1763 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1764 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1769 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1770 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1775 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1776 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1787 .custData = {"x112-041-f0000"},
1803 * bit0 - enable tx temp comp - disabled
1804 * bit1 - enable tx volt comp - disabled
1805 * bit2 - enable fastclock - enabled
1806 * bit3 - enable doubling - enabled
1807 * bit4 - enable internal regulator - disabled
1808 * bit5 - enable pa predistortion - disabled
1810 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1855 .noiseFloorThreshCh = {-1, 0, 0},
1864 .adcDesiredSize = -30,
1913 /* 1L-5L,5S,11L,11s */
1918 /* 6-24,36,48,54 */
2020 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2021 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2022 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2024 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2025 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2026 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2028 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2029 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2030 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2032 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2033 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2034 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2058 .noiseFloorThreshCh = {-1, 0, 0},
2067 .adcDesiredSize = -30,
2162 /* 6-24,36,48,54 */
2174 * 0_8_16,1-3_9-11_17-19,
2188 * 0_8_16,1-3_9-11_17-19,
2306 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2307 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2312 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2313 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2318 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2319 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2324 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2325 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2330 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2331 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2336 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2337 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2342 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2343 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2348 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2349 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2354 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2355 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2365 .custData = {"h116-041-f0000"},
2381 * bit0 - enable tx temp comp - disabled
2382 * bit1 - enable tx volt comp - disabled
2383 * bit2 - enable fastClock - enabled
2384 * bit3 - enable doubling - enabled
2385 * bit4 - enable internal regulator - disabled
2386 * bit5 - enable pa predistortion - disabled
2388 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2433 .noiseFloorThreshCh = {-1, 0, 0},
2442 .adcDesiredSize = -30,
2491 /* 1L-5L,5S,11L,11S */
2496 /* 6-24,36,48,54 */
2598 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2599 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2600 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2602 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2603 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2604 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2606 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2607 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2608 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2610 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2611 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2612 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2636 .noiseFloorThreshCh = {-1, 0, 0},
2645 .adcDesiredSize = -30,
2740 /* 6-24,36,48,54 */
2752 * 0_8_16,1-3_9-11_17-19,
2766 * 0_8_16,1-3_9-11_17-19,
2884 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2885 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2890 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2891 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2896 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2897 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2902 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2903 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2908 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2909 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2914 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2915 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2920 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2921 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2926 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2927 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2932 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2933 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2953 if (ar9300_eep_templates[it]->templateVersion == id) in ar9003_eeprom_struct_find_by_id()
2967 bf = 2 * (yb - ya) * (x - xa) / (xb - xa); in interpolate()
2976 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ath9k_hw_ar9300_get_eeprom()
2977 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; in ath9k_hw_ar9300_get_eeprom()
2981 return get_unaligned_be16(eep->macAddr); in ath9k_hw_ar9300_get_eeprom()
2983 return get_unaligned_be16(eep->macAddr + 2); in ath9k_hw_ar9300_get_eeprom()
2985 return get_unaligned_be16(eep->macAddr + 4); in ath9k_hw_ar9300_get_eeprom()
2987 return le16_to_cpu(pBase->regDmn[0]); in ath9k_hw_ar9300_get_eeprom()
2989 return pBase->deviceCap; in ath9k_hw_ar9300_get_eeprom()
2991 return pBase->opCapFlags.opFlags; in ath9k_hw_ar9300_get_eeprom()
2993 return pBase->rfSilent; in ath9k_hw_ar9300_get_eeprom()
2995 return (pBase->txrxMask >> 4) & 0xf; in ath9k_hw_ar9300_get_eeprom()
2997 return pBase->txrxMask & 0xf; in ath9k_hw_ar9300_get_eeprom()
2999 return !!(pBase->featureEnable & BIT(5)); in ath9k_hw_ar9300_get_eeprom()
3001 return (pBase->miscConfiguration >> 0x3) & 0x1; in ath9k_hw_ar9300_get_eeprom()
3006 return eep->base_ext1.ant_div_control; in ath9k_hw_ar9300_get_eeprom()
3008 return eep->modalHeader5G.antennaGain; in ath9k_hw_ar9300_get_eeprom()
3010 return eep->modalHeader2G.antennaGain; in ath9k_hw_ar9300_get_eeprom()
3048 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) { in ar9300_read_eeprom()
3054 * Since we're reading the bytes in reverse order from a little-endian in ar9300_read_eeprom()
3056 * the 16-bit word at that address in ar9300_read_eeprom()
3059 if (!ar9300_eeprom_read_byte(ah, address--, buffer++)) in ar9300_read_eeprom()
3062 count--; in ar9300_read_eeprom()
3069 address -= 2; in ar9300_read_eeprom()
3104 int offset = 8 * ((address - i) % 4); in ar9300_read_otp()
3105 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data)) in ar9300_read_otp()
3196 return -1; in ar9300_compress_decision()
3210 return -1; in ar9300_compress_decision()
3222 return -1; in ar9300_compress_decision()
3255 return -EIO; in ar9300_eeprom_restore_flash()
3263 * Returns -1 on error.
3286 return -EIO; in ar9300_eeprom_restore_internal()
3290 txrx = eep->baseEepHeader.txrxMask; in ar9300_eeprom_restore_internal()
3297 return -ENOMEM; in ar9300_eeprom_restore_internal()
3357 cptr -= COMP_HDR_LEN; in ar9300_eeprom_restore_internal()
3374 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN); in ar9300_eeprom_restore_internal()
3382 return -1; in ar9300_eeprom_restore_internal()
3387 * This function destroys any existing in-memory structure
3392 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep; in ath9k_hw_ar9300_fill_eeprom()
3405 PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0])); in ar9003_dump_modal_eeprom()
3406 PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1])); in ar9003_dump_modal_eeprom()
3407 PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2])); in ar9003_dump_modal_eeprom()
3408 PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon)); in ar9003_dump_modal_eeprom()
3409 PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2)); in ar9003_dump_modal_eeprom()
3410 PR_EEP("Ant. Gain", modal_hdr->antennaGain); in ar9003_dump_modal_eeprom()
3411 PR_EEP("Switch Settle", modal_hdr->switchSettling); in ar9003_dump_modal_eeprom()
3412 PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]); in ar9003_dump_modal_eeprom()
3413 PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]); in ar9003_dump_modal_eeprom()
3414 PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]); in ar9003_dump_modal_eeprom()
3415 PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]); in ar9003_dump_modal_eeprom()
3416 PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]); in ar9003_dump_modal_eeprom()
3417 PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]); in ar9003_dump_modal_eeprom()
3418 PR_EEP("Temp Slope", modal_hdr->tempSlope); in ar9003_dump_modal_eeprom()
3419 PR_EEP("Volt Slope", modal_hdr->voltSlope); in ar9003_dump_modal_eeprom()
3420 PR_EEP("spur Channels0", modal_hdr->spurChans[0]); in ar9003_dump_modal_eeprom()
3421 PR_EEP("spur Channels1", modal_hdr->spurChans[1]); in ar9003_dump_modal_eeprom()
3422 PR_EEP("spur Channels2", modal_hdr->spurChans[2]); in ar9003_dump_modal_eeprom()
3423 PR_EEP("spur Channels3", modal_hdr->spurChans[3]); in ar9003_dump_modal_eeprom()
3424 PR_EEP("spur Channels4", modal_hdr->spurChans[4]); in ar9003_dump_modal_eeprom()
3425 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]); in ar9003_dump_modal_eeprom()
3426 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]); in ar9003_dump_modal_eeprom()
3427 PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]); in ar9003_dump_modal_eeprom()
3428 PR_EEP("Quick Drop", modal_hdr->quick_drop); in ar9003_dump_modal_eeprom()
3429 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff); in ar9003_dump_modal_eeprom()
3430 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl); in ar9003_dump_modal_eeprom()
3431 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart); in ar9003_dump_modal_eeprom()
3432 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn); in ar9003_dump_modal_eeprom()
3433 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn); in ar9003_dump_modal_eeprom()
3434 PR_EEP("txClip", modal_hdr->txClip); in ar9003_dump_modal_eeprom()
3435 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize); in ar9003_dump_modal_eeprom()
3443 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_dump_cal_data()
3450 pBase = &eep->baseEepHeader; in ar9003_dump_cal_data()
3458 if (!((pBase->txrxMask >> i) & 1)) in ar9003_dump_cal_data()
3461 len += scnprintf(buf + len, size - len, "Chain %d\n", i); in ar9003_dump_cal_data()
3463 len += scnprintf(buf + len, size - len, in ar9003_dump_cal_data()
3468 cal_pier = &eep->calPierData2G[i][j]; in ar9003_dump_cal_data()
3469 freq = 2300 + eep->calFreqPier2G[j]; in ar9003_dump_cal_data()
3471 cal_pier = &eep->calPierData5G[i][j]; in ar9003_dump_cal_data()
3472 freq = 4800 + eep->calFreqPier5G[j] * 5; in ar9003_dump_cal_data()
3475 len += scnprintf(buf + len, size - len, in ar9003_dump_cal_data()
3478 len += scnprintf(buf + len, size - len, in ar9003_dump_cal_data()
3480 cal_pier->refPower, in ar9003_dump_cal_data()
3481 cal_pier->voltMeas, in ar9003_dump_cal_data()
3482 cal_pier->tempMeas, in ar9003_dump_cal_data()
3483 cal_pier->rxTempMeas ? in ar9003_dump_cal_data()
3484 N2DBM(cal_pier->rxNoisefloorCal) : 0, in ar9003_dump_cal_data()
3485 cal_pier->rxTempMeas ? in ar9003_dump_cal_data()
3486 N2DBM(cal_pier->rxNoisefloorPower) : 0, in ar9003_dump_cal_data()
3487 cal_pier->rxTempMeas); in ar9003_dump_cal_data()
3497 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ath9k_hw_ar9003_dump_eeprom()
3501 len += scnprintf(buf + len, size - len, in ath9k_hw_ar9003_dump_eeprom()
3504 &eep->modalHeader2G); in ath9k_hw_ar9003_dump_eeprom()
3506 len += scnprintf(buf + len, size - len, "Calibration data\n"); in ath9k_hw_ar9003_dump_eeprom()
3509 len += scnprintf(buf + len, size - len, in ath9k_hw_ar9003_dump_eeprom()
3512 &eep->modalHeader5G); in ath9k_hw_ar9003_dump_eeprom()
3514 len += scnprintf(buf + len, size - len, "Calibration data\n"); in ath9k_hw_ar9003_dump_eeprom()
3520 pBase = &eep->baseEepHeader; in ath9k_hw_ar9003_dump_eeprom()
3522 PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion); in ath9k_hw_ar9003_dump_eeprom()
3523 PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0])); in ath9k_hw_ar9003_dump_eeprom()
3524 PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1])); in ath9k_hw_ar9003_dump_eeprom()
3525 PR_EEP("TX Mask", (pBase->txrxMask >> 4)); in ath9k_hw_ar9003_dump_eeprom()
3526 PR_EEP("RX Mask", (pBase->txrxMask & 0x0f)); in ath9k_hw_ar9003_dump_eeprom()
3527 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags & in ath9k_hw_ar9003_dump_eeprom()
3529 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags & in ath9k_hw_ar9003_dump_eeprom()
3531 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags & in ath9k_hw_ar9003_dump_eeprom()
3533 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags & in ath9k_hw_ar9003_dump_eeprom()
3535 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags & in ath9k_hw_ar9003_dump_eeprom()
3537 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags & in ath9k_hw_ar9003_dump_eeprom()
3539 PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & in ath9k_hw_ar9003_dump_eeprom()
3541 PR_EEP("RF Silent", pBase->rfSilent); in ath9k_hw_ar9003_dump_eeprom()
3542 PR_EEP("BT option", pBase->blueToothOptions); in ath9k_hw_ar9003_dump_eeprom()
3543 PR_EEP("Device Cap", pBase->deviceCap); in ath9k_hw_ar9003_dump_eeprom()
3544 PR_EEP("Device Type", pBase->deviceType); in ath9k_hw_ar9003_dump_eeprom()
3545 PR_EEP("Power Table Offset", pBase->pwrTableOffset); in ath9k_hw_ar9003_dump_eeprom()
3546 PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]); in ath9k_hw_ar9003_dump_eeprom()
3547 PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]); in ath9k_hw_ar9003_dump_eeprom()
3548 PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0))); in ath9k_hw_ar9003_dump_eeprom()
3549 PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1))); in ath9k_hw_ar9003_dump_eeprom()
3550 PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2))); in ath9k_hw_ar9003_dump_eeprom()
3551 PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3))); in ath9k_hw_ar9003_dump_eeprom()
3552 PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4))); in ath9k_hw_ar9003_dump_eeprom()
3553 PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5))); in ath9k_hw_ar9003_dump_eeprom()
3554 PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0))); in ath9k_hw_ar9003_dump_eeprom()
3555 PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1))); in ath9k_hw_ar9003_dump_eeprom()
3556 PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1); in ath9k_hw_ar9003_dump_eeprom()
3557 PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio); in ath9k_hw_ar9003_dump_eeprom()
3558 PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio); in ath9k_hw_ar9003_dump_eeprom()
3559 PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio); in ath9k_hw_ar9003_dump_eeprom()
3560 PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio); in ath9k_hw_ar9003_dump_eeprom()
3561 PR_EEP("Tx Gain", pBase->txrxgain >> 4); in ath9k_hw_ar9003_dump_eeprom()
3562 PR_EEP("Rx Gain", pBase->txrxgain & 0xf); in ath9k_hw_ar9003_dump_eeprom()
3563 PR_EEP("SW Reg", le32_to_cpu(pBase->swreg)); in ath9k_hw_ar9003_dump_eeprom()
3565 len += scnprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress", in ath9k_hw_ar9003_dump_eeprom()
3566 ah->eeprom.ar9300_eep.macAddr); in ath9k_hw_ar9003_dump_eeprom()
3584 return ah->eeprom.ar9300_eep.eepromVersion; in ath9k_hw_ar9300_get_eeprom_ver()
3596 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_modal_header()
3599 return &eep->modalHeader2G; in ar9003_modal_header()
3601 return &eep->modalHeader5G; in ar9003_modal_header()
3606 int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl; in ar9003_hw_xpa_bias_level_apply()
3625 return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt); in ar9003_switch_com_spdt_get()
3630 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon); in ar9003_hw_ant_ctrl_common_get()
3635 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2); in ar9003_hw_ant_ctrl_common_2_get()
3641 __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain]; in ar9003_hw_ant_ctrl_chain_get()
3648 struct ath9k_hw_capabilities *pCap = &ah->caps; in ar9003_hw_ant_ctrl_apply()
3658 if (ah->config.xlna_gpio) in ar9003_hw_ant_ctrl_apply()
3659 gpio = ah->config.xlna_gpio; in ar9003_hw_ant_ctrl_apply()
3701 if (AR_SREV_9485(ah) && common->bt_ant_diversity) { in ar9003_hw_ant_ctrl_apply()
3703 value |= ah->config.ant_ctrl_comm2g_switch_enable; in ar9003_hw_ant_ctrl_apply()
3708 if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0x2)) { in ar9003_hw_ant_ctrl_apply()
3715 if ((ah->rxchainmask & BIT(chain)) || in ar9003_hw_ant_ctrl_apply()
3716 (ah->txchainmask & BIT(chain))) { in ar9003_hw_ant_ctrl_apply()
3737 if (AR_SREV_9485(ah) && common->bt_ant_diversity) in ar9003_hw_ant_ctrl_apply()
3741 if (common->bt_ant_diversity) { in ar9003_hw_ant_ctrl_apply()
3771 && common->bt_ant_diversity) in ar9003_hw_ant_ctrl_apply()
3776 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) { in ar9003_hw_ant_ctrl_apply()
3779 * clear bits 25-30 main_lnaconf, alt_lnaconf, in ar9003_hw_ant_ctrl_apply()
3798 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_drive_strength_apply()
3799 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; in ar9003_hw_drive_strength_apply()
3803 drive_strength = pBase->miscConfiguration & BIT(0); in ar9003_hw_drive_strength_apply()
3843 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_atten_chain_get()
3847 return eep->modalHeader2G.xatten1DB[chain]; in ar9003_hw_atten_chain_get()
3848 else if (eep->base_ext2.xatten1DBLow[chain] != 0) { in ar9003_hw_atten_chain_get()
3849 t[0] = eep->base_ext2.xatten1DBLow[chain]; in ar9003_hw_atten_chain_get()
3851 t[1] = eep->modalHeader5G.xatten1DB[chain]; in ar9003_hw_atten_chain_get()
3853 t[2] = eep->base_ext2.xatten1DBHigh[chain]; in ar9003_hw_atten_chain_get()
3855 value = ar9003_hw_power_interpolate((s32) chan->channel, in ar9003_hw_atten_chain_get()
3859 return eep->modalHeader5G.xatten1DB[chain]; in ar9003_hw_atten_chain_get()
3871 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_atten_chain_get_margin()
3875 return eep->modalHeader2G.xatten1Margin[chain]; in ar9003_hw_atten_chain_get_margin()
3876 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) { in ar9003_hw_atten_chain_get_margin()
3877 t[0] = eep->base_ext2.xatten1MarginLow[chain]; in ar9003_hw_atten_chain_get_margin()
3879 t[1] = eep->modalHeader5G.xatten1Margin[chain]; in ar9003_hw_atten_chain_get_margin()
3881 t[2] = eep->base_ext2.xatten1MarginHigh[chain]; in ar9003_hw_atten_chain_get_margin()
3883 value = ar9003_hw_power_interpolate((s32) chan->channel, in ar9003_hw_atten_chain_get_margin()
3887 return eep->modalHeader5G.xatten1Margin[chain]; in ar9003_hw_atten_chain_get_margin()
3902 if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0x2)) { in ar9003_hw_atten_apply()
3915 if (ah->txchainmask & BIT(i)) { in ar9003_hw_atten_apply()
3922 ah->config.xatten_margin_cfg) in ar9003_hw_atten_apply()
3927 if (ah->config.alt_mingainidx) in ar9003_hw_atten_apply()
3944 if (timeout-- == 0) in is_pmu_set()
3955 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_internal_regulator_apply()
3956 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; in ar9003_hw_internal_regulator_apply()
3959 if (pBase->featureEnable & BIT(4)) { in ar9003_hw_internal_regulator_apply()
3969 if (ah->is_clk_25mhz) { in ar9003_hw_internal_regulator_apply()
4004 reg_val = le32_to_cpu(pBase->swreg); in ar9003_hw_internal_regulator_apply()
4011 reg_val = le32_to_cpu(pBase->swreg); in ar9003_hw_internal_regulator_apply()
4050 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_apply_tuning_caps()
4051 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0]; in ar9003_hw_apply_tuning_caps()
4056 if (eep->baseEepHeader.featureEnable & 0x40) { in ar9003_hw_apply_tuning_caps()
4067 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_quick_drop_apply()
4068 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; in ar9003_hw_quick_drop_apply()
4072 if (!(pBase->miscConfiguration & BIT(4))) in ar9003_hw_quick_drop_apply()
4077 quick_drop = eep->modalHeader2G.quick_drop; in ar9003_hw_quick_drop_apply()
4079 t[0] = eep->base_ext1.quick_drop_low; in ar9003_hw_quick_drop_apply()
4080 t[1] = eep->modalHeader5G.quick_drop; in ar9003_hw_quick_drop_apply()
4081 t[2] = eep->base_ext1.quick_drop_high; in ar9003_hw_quick_drop_apply()
4092 value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff; in ar9003_hw_txend_to_xpa_off_apply()
4102 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_xpa_timing_control_apply()
4105 if (!(eep->baseEepHeader.featureEnable & 0x80)) in ar9003_hw_xpa_timing_control_apply()
4115 xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn; in ar9003_hw_xpa_timing_control_apply()
4126 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_xlna_bias_strength_apply()
4129 if (!(eep->baseEepHeader.miscConfiguration & 0x40)) in ar9003_hw_xlna_bias_strength_apply()
4135 bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength; in ar9003_hw_xlna_bias_strength_apply()
4148 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_get_thermometer()
4149 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; in ar9003_hw_get_thermometer()
4150 int thermometer = (pBase->miscConfiguration >> 1) & 0x3; in ar9003_hw_get_thermometer()
4152 return --thermometer; in ar9003_hw_get_thermometer()
4157 struct ath9k_hw_capabilities *pCap = &ah->caps; in ar9003_hw_thermometer_apply()
4163 if (pCap->chip_chainmask & BIT(1)) in ar9003_hw_thermometer_apply()
4166 if (pCap->chip_chainmask & BIT(2)) in ar9003_hw_thermometer_apply()
4173 if (pCap->chip_chainmask & BIT(1)) { in ar9003_hw_thermometer_apply()
4178 if (pCap->chip_chainmask & BIT(2)) { in ar9003_hw_thermometer_apply()
4207 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_apply_minccapwr_thresh()
4217 if (!(eep->base_ext1.misc_enable & BIT(2))) in ar9003_hw_apply_minccapwr_thresh()
4220 if (!(eep->base_ext1.misc_enable & BIT(3))) in ar9003_hw_apply_minccapwr_thresh()
4225 if (!(ah->caps.tx_chainmask & BIT(chain))) in ar9003_hw_apply_minccapwr_thresh()
4228 val = ar9003_modal_header(ah, is2ghz)->noiseFloorThreshCh[chain]; in ar9003_hw_apply_minccapwr_thresh()
4245 ar9003_hw_quick_drop_apply(ah, chan->channel); in ath9k_hw_ar9300_set_board_values()
4283 dx = x - px[ip]; in ar9003_hw_power_interpolate()
4287 if (!hhave || dx > (x - hx)) { in ar9003_hw_power_interpolate()
4296 if (!lhave || dx < (x - lx)) { in ar9003_hw_power_interpolate()
4319 y = -(1 << 30); in ar9003_hw_power_interpolate()
4329 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_eeprom_get_tgt_pwr()
4335 pEepromTargetPwr = eep->calTargetPower2G; in ar9003_hw_eeprom_get_tgt_pwr()
4336 pFreqBin = eep->calTarget_freqbin_2G; in ar9003_hw_eeprom_get_tgt_pwr()
4339 pEepromTargetPwr = eep->calTargetPower5G; in ar9003_hw_eeprom_get_tgt_pwr()
4340 pFreqBin = eep->calTarget_freqbin_5G; in ar9003_hw_eeprom_get_tgt_pwr()
4365 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_eeprom_get_ht20_tgt_pwr()
4371 pEepromTargetPwr = eep->calTargetPower2GHT20; in ar9003_hw_eeprom_get_ht20_tgt_pwr()
4372 pFreqBin = eep->calTarget_freqbin_2GHT20; in ar9003_hw_eeprom_get_ht20_tgt_pwr()
4375 pEepromTargetPwr = eep->calTargetPower5GHT20; in ar9003_hw_eeprom_get_ht20_tgt_pwr()
4376 pFreqBin = eep->calTarget_freqbin_5GHT20; in ar9003_hw_eeprom_get_ht20_tgt_pwr()
4401 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_eeprom_get_ht40_tgt_pwr()
4407 pEepromTargetPwr = eep->calTargetPower2GHT40; in ar9003_hw_eeprom_get_ht40_tgt_pwr()
4408 pFreqBin = eep->calTarget_freqbin_2GHT40; in ar9003_hw_eeprom_get_ht40_tgt_pwr()
4411 pEepromTargetPwr = eep->calTargetPower5GHT40; in ar9003_hw_eeprom_get_ht40_tgt_pwr()
4412 pFreqBin = eep->calTarget_freqbin_5GHT40; in ar9003_hw_eeprom_get_ht40_tgt_pwr()
4436 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_eeprom_get_cck_tgt_pwr()
4437 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck; in ar9003_hw_eeprom_get_cck_tgt_pwr()
4438 u8 *pFreqBin = eep->calTarget_freqbin_Cck; in ar9003_hw_eeprom_get_cck_tgt_pwr()
4514 /* Write the power for duplicated frames - HT40 */ in ar9003_hw_tx_power_regwrite()
4526 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ in ar9003_hw_tx_power_regwrite()
4563 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) in ar9003_hw_tx_power_regwrite()
4731 u16 freq = chan->channel; in ar9003_hw_get_target_power_eeprom()
4760 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_cal_pier_get()
4767 return -1; in ar9003_hw_cal_pier_get()
4775 return -1; in ar9003_hw_cal_pier_get()
4778 pCalPier = &(eep->calFreqPier2G[ipier]); in ar9003_hw_cal_pier_get()
4779 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]); in ar9003_hw_cal_pier_get()
4785 return -1; in ar9003_hw_cal_pier_get()
4787 pCalPier = &(eep->calFreqPier5G[ipier]); in ar9003_hw_cal_pier_get()
4788 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]); in ar9003_hw_cal_pier_get()
4792 *pcorrection = pCalPierStruct->refPower; in ar9003_hw_cal_pier_get()
4793 *ptemperature = pCalPierStruct->tempMeas; in ar9003_hw_cal_pier_get()
4794 *pvoltage = pCalPierStruct->voltMeas; in ar9003_hw_cal_pier_get()
4795 *pnf_cal = pCalPierStruct->rxTempMeas ? in ar9003_hw_cal_pier_get()
4796 N2DBM(pCalPierStruct->rxNoisefloorCal) : 0; in ar9003_hw_cal_pier_get()
4797 *pnf_power = pCalPierStruct->rxTempMeas ? in ar9003_hw_cal_pier_get()
4798 N2DBM(pCalPierStruct->rxNoisefloorPower) : 0; in ar9003_hw_cal_pier_get()
4809 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_power_control_override()
4815 if (ah->caps.tx_chainmask & BIT(1)) in ar9003_hw_power_control_override()
4819 if (ah->caps.tx_chainmask & BIT(2)) in ar9003_hw_power_control_override()
4828 if (ah->caps.tx_chainmask & BIT(1)) in ar9003_hw_power_control_override()
4832 if (ah->caps.tx_chainmask & BIT(2)) in ar9003_hw_power_control_override()
4842 temp_slope = eep->modalHeader2G.tempSlope; in ar9003_hw_power_control_override()
4845 t[0] = eep->base_ext1.tempslopextension[2]; in ar9003_hw_power_control_override()
4846 t1[0] = eep->base_ext1.tempslopextension[3]; in ar9003_hw_power_control_override()
4847 t2[0] = eep->base_ext1.tempslopextension[4]; in ar9003_hw_power_control_override()
4850 t[1] = eep->modalHeader5G.tempSlope; in ar9003_hw_power_control_override()
4851 t1[1] = eep->base_ext1.tempslopextension[0]; in ar9003_hw_power_control_override()
4852 t2[1] = eep->base_ext1.tempslopextension[1]; in ar9003_hw_power_control_override()
4855 t[2] = eep->base_ext1.tempslopextension[5]; in ar9003_hw_power_control_override()
4856 t1[2] = eep->base_ext1.tempslopextension[6]; in ar9003_hw_power_control_override()
4857 t2[2] = eep->base_ext1.tempslopextension[7]; in ar9003_hw_power_control_override()
4870 if ((eep->baseEepHeader.miscConfiguration & 0x20) != 0) { in ar9003_hw_power_control_override()
4872 t[i] = eep->base_ext1.tempslopextension[i]; in ar9003_hw_power_control_override()
4873 f[i] = FBIN2FREQ(eep->calFreqPier5G[i], 0); in ar9003_hw_power_control_override()
4877 } else if (eep->base_ext2.tempSlopeLow != 0) { in ar9003_hw_power_control_override()
4878 t[0] = eep->base_ext2.tempSlopeLow; in ar9003_hw_power_control_override()
4880 t[1] = eep->modalHeader5G.tempSlope; in ar9003_hw_power_control_override()
4882 t[2] = eep->base_ext2.tempSlopeHigh; in ar9003_hw_power_control_override()
4887 temp_slope = eep->modalHeader5G.tempSlope; in ar9003_hw_power_control_override()
4893 u8 txmask = (eep->baseEepHeader.txrxMask & 0xf0) >> 4; in ar9003_hw_power_control_override()
4899 if (eep->baseEepHeader.featureEnable & 0x1) { in ar9003_hw_power_control_override()
4904 eep->base_ext2.tempSlopeLow); in ar9003_hw_power_control_override()
4912 eep->base_ext2.tempSlopeHigh); in ar9003_hw_power_control_override()
4993 fdiff = frequency - pfrequency; in ar9003_hw_calibration_apply()
5003 (frequency - hfrequency[ichain])) { in ar9003_hw_calibration_apply()
5021 (frequency - lfrequency[ichain])) { in ar9003_hw_calibration_apply()
5058 else if (frequency - lfrequency[ichain] < 1000) { in ar9003_hw_calibration_apply()
5060 if (hfrequency[ichain] - frequency < 1000) { in ar9003_hw_calibration_apply()
5102 else if (hfrequency[ichain] - frequency < 1000) { in ar9003_hw_calibration_apply()
5127 ah->nf_2g.cal[ichain] = nf_cal[ichain]; in ar9003_hw_calibration_apply()
5128 ah->nf_2g.pwr[ichain] = nf_pwr[ichain]; in ar9003_hw_calibration_apply()
5130 ah->nf_5g.cal[ichain] = nf_cal[ichain]; in ar9003_hw_calibration_apply()
5131 ah->nf_5g.pwr[ichain] = nf_pwr[ichain]; in ar9003_hw_calibration_apply()
5142 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G; in ar9003_hw_get_direct_edge_power()
5143 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G; in ar9003_hw_get_direct_edge_power()
5157 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G; in ar9003_hw_get_indirect_edge_power()
5158 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G; in ar9003_hw_get_indirect_edge_power()
5161 &eep->ctl_freqbin_2G[idx][0] : in ar9003_hw_get_indirect_edge_power()
5162 &eep->ctl_freqbin_5G[idx][0]; in ar9003_hw_get_indirect_edge_power()
5165 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq && in ar9003_hw_get_indirect_edge_power()
5166 CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1])) in ar9003_hw_get_indirect_edge_power()
5167 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]); in ar9003_hw_get_indirect_edge_power()
5169 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq && in ar9003_hw_get_indirect_edge_power()
5170 CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1])) in ar9003_hw_get_indirect_edge_power()
5171 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]); in ar9003_hw_get_indirect_edge_power()
5178 * Find the maximum conformance test limit for the given channel and CTL info
5185 &eep->ctl_freqbin_2G[idx][0] : in ar9003_hw_get_max_edge_power()
5186 &eep->ctl_freqbin_5G[idx][0]; in ar9003_hw_get_max_edge_power()
5212 * Leave loop - no more affecting edges possible in in ar9003_hw_get_max_edge_power()
5232 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep; in ar9003_hw_set_power_per_rate_table()
5257 /* Setup for CTL modes */ in ar9003_hw_set_power_per_rate_table()
5260 ARRAY_SIZE(ctlModesFor11g) - in ar9003_hw_set_power_per_rate_table()
5264 /* All 2G CTL's */ in ar9003_hw_set_power_per_rate_table()
5267 /* Setup for CTL modes */ in ar9003_hw_set_power_per_rate_table()
5269 numCtlModes = ARRAY_SIZE(ctlModesFor11a) - in ar9003_hw_set_power_per_rate_table()
5273 /* All 5G CTL's */ in ar9003_hw_set_power_per_rate_table()
5283 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. in ar9003_hw_set_power_per_rate_table()
5296 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n", in ar9003_hw_set_power_per_rate_table()
5300 /* walk through each CTL index stored in EEPROM */ in ar9003_hw_set_power_per_rate_table()
5302 ctlIndex = pEepData->ctlIndex_2G; in ar9003_hw_set_power_per_rate_table()
5305 ctlIndex = pEepData->ctlIndex_5G; in ar9003_hw_set_power_per_rate_table()
5312 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n", in ar9003_hw_set_power_per_rate_table()
5314 chan->channel); in ar9003_hw_set_power_per_rate_table()
5335 * Find the minimum of all CTL in ar9003_hw_set_power_per_rate_table()
5353 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n", in ar9003_hw_set_power_per_rate_table()
5357 /* Apply ctl mode to correct target power set */ in ar9003_hw_set_power_per_rate_table()
5401 } /* end ctl mode checking */ in ar9003_hw_set_power_per_rate_table()
5411 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2; in mcsidx_to_tgtpwridx()
5438 ah->paprd_target_power = targetPowerValT2[i]; in ar9003_paprd_set_txpower()
5457 * Get target powers from EEPROM - our baseline for TX Power in ath9k_hw_ar9300_set_txpower()
5462 ah->paprd_ratemask = in ath9k_hw_ar9300_set_txpower()
5466 ah->paprd_ratemask_ht40 = in ath9k_hw_ar9300_set_txpower()
5474 if (!ah->paprd_table_write_done) { in ath9k_hw_ar9300_set_txpower()
5479 if (ah->paprd_ratemask & (1 << i)) { in ath9k_hw_ar9300_set_txpower()
5483 targetPowerValT2[pwr_idx] -= in ath9k_hw_ar9300_set_txpower()
5502 if ((ah->paprd_ratemask & (1 << i)) && in ath9k_hw_ar9300_set_txpower()
5503 (abs(targetPowerValT2[i] - in ath9k_hw_ar9300_set_txpower()
5506 ah->paprd_ratemask &= ~(1 << i); in ath9k_hw_ar9300_set_txpower()
5513 regulatory->max_power_level = 0; in ath9k_hw_ar9300_set_txpower()
5515 if (targetPowerValT2[i] > regulatory->max_power_level) in ath9k_hw_ar9300_set_txpower()
5516 regulatory->max_power_level = targetPowerValT2[i]; in ath9k_hw_ar9300_set_txpower()
5531 ar9003_hw_calibration_apply(ah, chan->channel); in ath9k_hw_ar9300_set_txpower()
5537 if (ah->tpc_enabled) { in ath9k_hw_ar9300_set_txpower()
5567 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_get_tx_gain_idx()
5569 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */ in ar9003_hw_get_tx_gain_idx()
5574 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_get_rx_gain_idx()
5576 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */ in ar9003_hw_get_rx_gain_idx()
5581 return ar9003_modal_header(ah, is2ghz)->spurChans; in ar9003_get_spur_chan_ptr()
5586 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->papdRateMaskHt20); in ar9003_get_paprd_rate_mask_ht20()
5591 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->papdRateMaskHt40); in ar9003_get_paprd_rate_mask_ht40()
5603 if (chan->channel >= 5700) in ar9003_get_paprd_scale_factor()
5606 else if (chan->channel >= 5400) in ar9003_get_paprd_scale_factor()
5617 return ah->eeprom.ar9300_eep.baseEepHeader.opCapFlags.eepMisc; in ar9003_get_eepmisc()