| /linux-6.14.4/Documentation/devicetree/bindings/interrupt-controller/ |
| D | fsl,mu-msi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <[email protected]>
16 for one processor (A side) to signal the other processor (B side) using
20 different clocks (from each side of the different peripheral buses).
21 Therefore, the MU must synchronize the accesses from one side to the
23 registers (Processor A-side, Processor B-side).
28 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
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| /linux-6.14.4/Documentation/devicetree/bindings/mailbox/ |
| D | fsl,mu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <[email protected]>
16 for one processor to signal the other processor using interrupts.
19 different clocks (from each side of the different peripheral buses).
20 Therefore, the MU must synchronize the accesses from one side to the
22 registers (Processor A-facing, Processor B-facing).
27 - const: fsl,imx6sx-mu
28 - const: fsl,imx7ulp-mu
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| /linux-6.14.4/tools/perf/pmu-events/arch/powerpc/power9/ |
| D | other.json | 45 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …
50 …dified (M) data from another core's ECO L3 on the same chip due to a data side request. When using…
65 "BriefDescription": "Read-write data cache collisions"
90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core"
95 …"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory d…
145 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st…
200 "BriefDescription": "Read-write data cache collisions"
255 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st…
280 …-word boundary, which causes it to require an additional slice than than what normally would be re…
300 "BriefDescription": "I-cache Invalidates sent over the realod bus to the core"
[all …]
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| /linux-6.14.4/arch/arm/kernel/ |
| D | head-nommu.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/head-nommu.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2006 Hyok S. Choi
8 * Common kernel startup code (non-paged MM)
16 #include <asm/asm-offsets.h>
25 * ---------------------------
28 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
31 * See linux/arch/arm/tools/mach-types for the complete list of machine
46 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
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| D | entry-armv.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/entry-armv.S
6 * ARM700 fix by Matthew Godbolt (linux-[email protected])
9 * Low-level vector interface routines
19 #include <asm/glue-df.h>
20 #include <asm/glue-pf.h>
27 #include <asm/uaccess-asm.h>
30 #include "entry-header.S"
59 b 1f
71 ldr_va ip, processor, offset=PROCESSOR_PABT_FUNC
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| /linux-6.14.4/tools/perf/pmu-events/arch/powerpc/power8/ |
| D | other.json | 11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong …
113 …to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that re…
161 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d…
167 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d…
197 …ional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set thi…
203 …ional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set thi…
215 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
221 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
359 "BriefDescription": "IFU Finished a (non-branch) instruction",
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| /linux-6.14.4/drivers/irqchip/ |
| D | irq-imx-mu-msi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 * Based on drivers/mailbox/imx-mailbox.c
27 #include "irq-msi-lib.h"
52 #define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
53 #define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
75 iowrite32(val, msi_data->regs + offs); in imx_mu_write()
80 return ioread32(msi_data->regs + offs); in imx_mu_read()
88 raw_spin_lock_irqsave(&msi_data->lock, flags); in imx_mu_xcr_rmw()
89 val = imx_mu_read(msi_data, msi_data->cfg->xCR[type]); in imx_mu_xcr_rmw()
92 imx_mu_write(msi_data, val, msi_data->cfg->xCR[type]); in imx_mu_xcr_rmw()
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| /linux-6.14.4/drivers/eisa/ |
| D | eisa.ids | 6 # Marc Zyngier <maz@wild-wind.fr.eu.org>
10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter"
11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter"
12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter"
13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter"
14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
25 ACE7010 "ACME Multi-Function Board"
39 ACR1711 "AcerFrame 1000 486/33 SYSTEM-2"
41 ACR3211 "AcerFrame 3000MP 486 SYSTEM-1"
[all …]
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| /linux-6.14.4/drivers/cpufreq/ |
| D | speedstep-lib.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) 2002 - 2003 Dominik Brodowski <[email protected]>
20 #include "speedstep-lib.h"
22 #define PFX "speedstep-lib: "
31 * GET PROCESSOR CORE SPEED IN KHZ *
34 static unsigned int pentium3_get_frequency(enum speedstep_processor processor) in pentium3_get_frequency() argument
59 /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */ in pentium3_get_frequency()
61 unsigned int value; /* Front Side Bus speed in MHz */ in pentium3_get_frequency()
74 /* read MSR 0x2a - we only need the low 32 bits */ in pentium3_get_frequency()
76 pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp); in pentium3_get_frequency()
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/remoteproc/ |
| D | st,stm32-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/st,stm32-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 remote processor controller
14 - Fabien Dessenne <[email protected]>
15 - Arnaud Pouliquen <[email protected]>
19 const: st,stm32mp1-m4
24 processor.
31 reset-names:
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| /linux-6.14.4/Documentation/arch/arm/ |
| D | cluster-pm-race-avoidance.rst | 2 Cluster-wide Power-up/power-down race avoidance algorithm
16 ---------
29 cluster-level operations are only performed when it is truly safe to do
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
50 - DOWN
51 - COMING_UP
52 - UP
53 - GOING_DOWN
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| /linux-6.14.4/Documentation/input/devices/ |
| D | walkera0701.rst | 2 Walkera WK-0701 transmitter
5 Walkera WK-0701 transmitter is supplied with a ready to fly Walkera
10 http://zub.fei.tuke.sk/walkera-wk0701/
13 cg-clone http://zub.fei.tuke.sk/GIT/walkera0701-joystick
19 At back side of transmitter S-video connector can be found. Modulation
20 pulses from processor to HF part can be found at pin 2 of this connector,
26 Walkera WK-0701 TX S-VIDEO connector::
28 (back side of TX)
29 __ __ S-video: canon25
34 | [___] | |/| B |\
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| /linux-6.14.4/arch/arm/mach-at91/ |
| D | pm_suspend.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-at91/pm_slow_clock.S
13 #include "pm_data-offsets.h"
16 .arch armv7-a
32 * Side effects: overwrites r7, r8
39 b 2f
45 bne 2b
51 * Side effects: overwrites r7
56 beq 1b
62 * Side effects: overwrites r7
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| /linux-6.14.4/Documentation/core-api/ |
| D | cachetlb.rst | 9 describes its intended purpose, and what side effect is expected
12 The side effects described below are stated for a uniprocessor
13 implementation, and what is to happen on that single processor. The
15 definition such that the side effect for a particular interface occurs
25 virtual-->physical address translations obtained from the software
59 modifications for the address space 'vma->vm_mm' in the range
60 'start' to 'end-1' will be visible to the cpu. That is, after
62 virtual addresses in the range 'start' to 'end-1'.
78 address space is available via vma->vm_mm. Also, one may
79 test (vma->vm_flags & VM_EXEC) to see if this region is
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| /linux-6.14.4/arch/x86/kernel/acpi/ |
| D | boot.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * boot.c - Architecture-Specific Low-Level ACPI Boot Support
22 #include <linux/efi-bgrt.h>
75 * Hotplug side:
76 * ->device_hotplug_lock
77 * ->acpi_ioapic_lock
78 * ->ioapic_lock
79 * Interrupt mapping side:
80 * ->acpi_ioapic_lock
81 * ->ioapic_mutex
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| /linux-6.14.4/drivers/usb/gadget/udc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
5 # (b) the gadget driver using it.
7 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
11 # - Some systems have both kinds of controllers.
13 # With help from a special transceiver and a "Mini-AB" jack, systems with
14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
22 # - integrated/SOC controllers first
23 # - licensed IP used in both SOC and discrete versions
[all …]
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| /linux-6.14.4/include/linux/ |
| D | rcupdate.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Read-Copy Update mechanism for mutual exclusion
15 * For detailed explanation of Read-Copy Update mechanism see -
31 #include <asm/processor.h>
34 #define ULONG_CMP_GE(a, b) (ULONG_MAX / 2 >= (a) - (b)) argument
35 #define ULONG_CMP_LT(a, b) (ULONG_MAX / 2 < (a) - (b)) argument
38 #define RCU_SEQ_STATE_MASK ((1 << RCU_SEQ_CTR_SHIFT) - 1)
50 // not-yet-completed RCU grace periods.
54 * same_state_synchronize_rcu - Are two old-state values identical?
55 * @oldstate1: First old-state value.
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| /linux-6.14.4/arch/powerpc/platforms/powermac/ |
| D | udbg_scc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2001-2005 PPC 64 Team, IBM Corp
10 #include <asm/processor.h>
40 return -1; in udbg_scc_getc_poll()
42 return -1; in udbg_scc_getc_poll()
52 return -1; in udbg_scc_getc()
80 path = of_get_property(of_chosen, "linux,stdout-path", NULL); in udbg_scc_init()
88 if (of_node_name_eq(ch, "ch-a")) { in udbg_scc_init()
98 /* Get address within mac-io ASIC */ in udbg_scc_init()
104 /* Get address of mac-io PCI itself */ in udbg_scc_init()
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| /linux-6.14.4/arch/x86/boot/compressed/ |
| D | efi_mixed.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Early support for invoking 32-bit EFI services from a 64-bit kernel.
8 * restore the firmware's 32-bit GDT and IDT before we make EFI service
11 * On the plus side, we don't have to worry about mangling 64-bit
12 * addresses into 32-bits because we're executing with an identity
13 * mapped pagetable and haven't transitioned to 64-bit virtual addresses
18 #include <asm/asm-offsets.h>
21 #include <asm/processor-flags.h>
28 * When booting in 64-bit mode on 32-bit EFI firmware, startup_64_mixed_mode()
31 * enter the kernel, it will either branch to the common 64-bit EFI stub
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| /linux-6.14.4/tools/perf/pmu-events/arch/x86/amdzen3/ |
| D | memory.json | 5 …"BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. St…
6 …-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older …
24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.",
36 … "BriefDescription": "The number of retired CLFLUSH instructions. This is a non-speculative event."
46 …"BriefDescription": "Load-op-Store Dispatch. Dispatch of a single op that performs a load from and…
84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full.",
91 …esses, although these are generally rare. Each increment represents an eight-byte access, although…
258 "BriefDescription": "Total Page Table Walks on I-side.",
276 "BriefDescription": "Total Page Table Walks on D-side.",
300 "BriefDescription": "The number of 64B misaligned (i.e., cacheline crossing) loads.",
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| /linux-6.14.4/Documentation/arch/powerpc/ |
| D | transactional_memory.rst | 36 b continue
43 b begin_move_money
47 Between these points the processor is in 'Transactional' state; any memory
49 transactional or non-transactional accesses within the system. In this
50 example, the transaction completes as though it were normal straight-line code
51 IF no other processor has touched SAVINGS_ACCT(r3) or CURRENT_ACCT(r3); an
69 - Conflicts with cache lines used by other processors
70 - Signals
71 - Context switches
72 - See the ISA for full documentation of everything that will abort transactions.
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| /linux-6.14.4/arch/mips/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
145 bool "Generic board-agnostic MIPS kernel"
202 bool "Alchemy processor based machines"
287 Build a generic DT-based kernel image that boots on select
288 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
380 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
381 DECstation porting pages on <http://decstation.unix-ag.org/>.
420 Olivetti M700-10 workstations.
457 bool "Loongson 32-bit family of machines"
460 This enables support for the Loongson-1 family of machines.
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| /linux-6.14.4/drivers/net/wireless/intel/iwlegacy/ |
| D | csr.h | 8 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
70 * low power states due to driver-invoked device resets
71 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
77 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
86 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
100 * 31-8: Reserved
101 * 7-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions
102 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
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| /linux-6.14.4/arch/sparc/include/asm/ |
| D | oplib_64.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
85 /* Enter the prom, with no chance of continuation for the stand-alone
90 /* Halt and power-off the machine. */
153 /* Load explicit I/D TLB entries into the calling processor. */
166 #define PROM_MAP_READ 0x0002 /* Readable - sw */
167 #define PROM_MAP_EXEC 0x0004 /* Executable - sw */
170 #define PROM_MAP_SE 0x0040 /* Side-Effects */
172 #define PROM_MAP_IE 0x0100 /* Invert-Endianness */
191 * Returns -1 on error (ie. no such property at this node).
196 * the number of bytes the prom put into your buffer or -1 on error.
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| /linux-6.14.4/include/hyperv/ |
| D | hvhdk.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
169 * N.B. The final processor feature bit in bank 0 is reserved to
174 /* N.B. Begin bank 1 processor features. */
224 /* Support for HV#1: (CPUID leaves 0x40000000 - 0x40000006)*/
228 u64 access_synic_regs : 1; /* SINT-related registers */
436 /* linux side we create long version of flags to use long bit ops on flags */
603 * Note these hypercalls have an 8-byte aligned variable header size as per the tlfs
609 /* HvGetSetVpStateLocalInterruptControllerState - APIC/GIC state */
654 * VP-dispatching thread in the root on return from HVCALL_DISPATCH_VP.
674 #define HV_GENERIC_SET_QWORD_COUNT(max) (((((max) - 1) >> 6) + 1) + 2)
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|