Lines Matching +full:processor +full:- +full:b +full:- +full:side
1 # SPDX-License-Identifier: GPL-2.0
145 bool "Generic board-agnostic MIPS kernel"
202 bool "Alchemy processor based machines"
287 Build a generic DT-based kernel image that boots on select
288 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
380 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
381 DECstation porting pages on <http://decstation.unix-ag.org/>.
420 Olivetti M700-10 workstations.
457 bool "Loongson 32-bit family of machines"
460 This enables support for the Loongson-1 family of machines.
462 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
467 bool "Loongson-2E/F family of machines"
470 This enables the support of early Loongson-2E/F family of machines.
473 bool "Loongson 64-bit family of machines"
508 This enables the support of Loongson-2/3 family of machines.
510 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
511 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
512 and Loongson-2F which will be removed), developed by the Institute
577 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
775 This is the SGI Indigo2 with R10000 processor. To compile a Linux
832 bool "Sibyte BCM91125C-CRhone"
842 bool "Sibyte BCM91125E-Rhone"
851 bool "Sibyte BCM91250A-SWARM"
864 bool "Sibyte BCM91250C2-LittleSur"
876 bool "Sibyte BCM91250E-Sentosa"
886 bool "Sibyte BCM91480B-BigSur"
935 The SNI RM200/300/400 are MIPS-based machines manufactured by
1014 This requires u-boot on the platform.
1029 source "arch/mips/sgi-ip27/Kconfig"
1032 source "arch/mips/cavium-octeon/Kconfig"
1310 bool "Loongson 64-bit CPU"
1332 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
1334 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1336 Loongson-2E/2F is not covered here and will be removed in future.
1343 The Loongson 2E processor implements the MIPS III instruction set
1354 The Loongson 2F processor implements the MIPS III instruction set
1357 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1362 bool "Loongson 1B"
1367 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
1377 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
1389 MIPS32 architecture. Most modern embedded systems with a 32-bit
1390 MIPS processor are based on a MIPS32 processor. If you know the
1391 specific type of processor in your system, choose those that one
1394 years so chances are you even have a MIPS32 Release 2 processor
1407 MIPS32 architecture. Most modern embedded systems with a 32-bit
1408 MIPS processor are based on a MIPS32 processor. If you know the
1409 specific type of processor in your system, choose those that one
1424 family, are based on a MIPS32r5 processor. If you own an older
1425 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
1440 family, are based on a MIPS32r6 processor. If you own an older
1441 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
1453 MIPS64 architecture. Many modern embedded systems with a 64-bit
1454 MIPS processor are based on a MIPS64 processor. If you know the
1455 specific type of processor in your system, choose those that one
1458 years so chances are you even have a MIPS64 Release 2 processor
1473 MIPS64 architecture. Many modern embedded systems with a 64-bit
1474 MIPS processor are based on a MIPS64 processor. If you know the
1475 specific type of processor in your system, choose those that one
1510 family, are based on a MIPS64r6 processor. If you own an older
1511 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
1528 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
1530 cache, IOCU/IOMMU (though might be unused depending on the system-
1555 MIPS Technologies R4300-series processors.
1564 MIPS Technologies R4000-series processors other than 4300, including
1582 MIPS Technologies R5000-series processors other than the Nevada.
1591 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
1601 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1612 MIPS Technologies R10000-series processors.
1633 bool "Cavium Octeon processor"
1647 The Cavium Octeon processor is a highly integrated chip containing
1648 many ethernet hardware widgets for networking tasks. The processor
1676 bool "New Loongson-3 CPU Enhancements"
1680 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1681 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1682 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1683 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1688 please say 'N' here. If you want a high-performance kernel to run on
1689 new Loongson-3 machines only, please say 'Y' here.
1692 bool "Loongson-3 LLSC Workarounds"
1696 Loongson-3 processors have the llsc issues which require workarounds.
1706 Loongson-3A R4 and newer have the CPUCFG instruction available for
1709 cores, back to Loongson-3A1000.
1757 than 40 bits. Note that this has the side effect of turning on
1758 64-bit addressing which in turn makes the PTEs 64-bit in size.
1777 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
1780 are needed. The workarounds have no significant side effect on them
1948 # CPU may reorder R->R, R->W, W->R, W->W
1956 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
2058 actually benefits from 64-bit processing or if your machine has
2060 menu if your system does not support both 32-bit and 64-bit kernels.
2063 bool "32-bit kernel"
2067 Select this option if you want to build a 32-bit kernel.
2070 bool "64-bit kernel"
2073 Select this option if you want to build a 64-bit kernel.
2098 This is only used if non-zero.
2125 # Support for a MIPS32 / MIPS64 style S-caches
2205 <http://www.imgtec.com/mips/mips-multithreading.asp>.
2226 bool "Dynamic FPU affinity for FP-intensive threads"
2231 bool "MIPS R2-to-R6 emulator"
2236 Choose this option if you want to run non-R6 MIPS userland code.
2239 The only reason this is a build-time option is to save ~14K from the
2411 # CPU non-features
2416 # - The `daddi' instruction fails to trap on overflow.
2417 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2420 # - The `daddiu' instruction can produce an incorrect result.
2421 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2423 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
2425 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
2426 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
2432 # - A double-word or a variable shift may give an incorrect result
2434 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2436 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
2439 # - A double-word or a variable shift may give an incorrect result
2441 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2444 # - An integer division may give an incorrect result if started in
2446 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2454 # - A double-word or a variable shift may give an incorrect result
2456 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
2457 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
2481 # interrupts during indexed I-cache flushes seems to be sufficient to deal
2533 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2535 # I-cache line worth of instructions being fetched may case spurious
2541 # may cause ll / sc and lld / scd sequences to execute non-atomically.
2550 # - Highmem only makes sense for the 32-bit kernel.
2551 # - The current highmem code will only work properly on physically indexed
2558 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
2582 This option must be set if a kernel might be executed on a MIPS16-
2584 words, it makes the kernel MIPS16-tolerant.
2603 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
2670 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
2671 EVA or 64-bit. The default is 16Mb.
2698 bool "Multi-Processing support"
2705 If you say N here, the kernel will run on uni- and multiprocessor
2714 See also the SMP-HOWTO available at
2720 bool "Support for hot-pluggable CPUs"
2754 int "Maximum number of CPUs (2-256)"
2764 kernel will support. The maximum supported value is 32 for 32-bit
2765 kernel and 64 for 64-bit kernels; the minimum value which makes
2769 This is purely to save memory - each supported CPU adds
2889 passed to the panic-ed kernel).
2892 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
2895 When this is enabled, the kernel will support use of 64-bit floating
2897 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
2898 32-bit MIPS systems this support is at the cost of increasing the
2901 will require 64-bit floating point, you may wish to reduce the size
2944 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
3039 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
3041 <http://www.linux-mips.org/wiki/DECstation>
3085 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
3098 64-bit binaries using 32-bit quantities for addressing and certain
3099 data that would normally be 64-bit. They are used in special
3106 depends on $(cc-option,-mno-branch-likely)
3108 # https://github.com/llvm/llvm-project/issues/61045