Lines Matching +full:processor +full:- +full:b +full:- +full:side
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/entry-armv.S
6 * ARM700 fix by Matthew Godbolt (linux-[email protected])
9 * Low-level vector interface routines
19 #include <asm/glue-df.h>
20 #include <asm/glue-pf.h>
27 #include <asm/uaccess-asm.h>
30 #include "entry-header.S"
59 b 1f
71 ldr_va ip, processor, offset=PROCESSOR_PABT_FUNC
81 @ Call the processor-specific abort handler:
83 @ r2 - pt_regs
84 @ r4 - aborted context pc
85 @ r5 - aborted context psr
91 ldr_va ip, processor, offset=PROCESSOR_DABT_FUNC
105 ARM( stmib sp, {r1 - lr} )
106 THUMB( stmia sp, {r0 - r12} )
114 b common_invalid
119 b common_invalid
124 b common_invalid
135 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
140 ldmia r0, {r4 - r6}
142 mov r7, #-1 @ "" "" "" ""
144 stmia r0, {r5 - r7} @ lr_<exception>,
148 b bad_mode
168 UNWIND(.save {r0 - pc} )
181 ARM( stmib sp, {r1 - r12} )
182 THUMB( stmia sp, {r0 - r12} ) @ No STMIB in Thumb-2
184 ldmia r0, {r3 - r5}
186 mov r6, #-1 @ "" "" "" ""
197 @ r2 - sp_svc
198 @ r3 - lr_svc
199 @ r4 - lr_<exception>, already fixed up for correct return/restart
200 @ r5 - spsr_<exception>
201 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
203 stmia r7, {r2 - r6}
252 b 1b
265 b do_undefinstr
331 stmfd sp!, {r1 - r2}
336 ldmfd sp!, {r1 - r2}
353 * EABI note: sp_svc is always 64-bit aligned here, so should PT_REGS_SIZE
364 ARM( stmib sp, {r1 - r12} )
365 THUMB( stmia sp, {r0 - r12} )
370 ldmia r0, {r3 - r5}
372 mov r6, #-1 @ "" "" "" ""
380 @ r4 - lr_<exception>, already fixed up for correct return/restart
381 @ r5 - spsr_<exception>
382 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
386 stmia r0, {r4 - r6}
388 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
435 b ret_from_exception
446 b ret_to_user_from_irq
472 b ret_from_exception
491 b ret_to_user
516 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
517 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
554 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
557 ldmia r4, {r4 - sl, fp, ip, lr} @ Load all regs saved previously
579 @ switches us to another stack, with few other side effects. In order
597 @ involving the PC, and decorate them with PC-relative group
608 str sp, [ip, #-4]! @ Preserve original SP value
616 str ip, [sp, #-8]! @ store original SP
655 * Each segment is 32-byte aligned and will be moved to the top of the high
673 .if (. - \sym) & 3
674 .rept 4 - (. - \sym) & 3
678 .rept (\size - (. - \sym)) / 4
706 beq 1b @ if no then retry
737 @ 1b = first critical insn, 2b = last critical insn.
738 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
740 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
742 rsbscs r8, r8, #(2b - 1b)
752 mov r0, #-1
795 @ 1b = first critical insn, 2b = last critical insn.
796 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
798 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
800 rsbscs r8, r8, #(2b - 1b)
807 mov r0, #-1
819 beq 1b
821 /* beware -- each __kuser slot must be 8 instructions max */
822 ALT_SMP(b __kuser_memory_barrier)
830 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
839 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
858 * SP points to a minimal amount of processor-private memory, the address
914 3: W(b) . + 4
916 bne 3b
920 b .Lvec_\name
947 b vector_und
965 .long __irq_invalid @ b
988 .long __dabt_invalid @ b
1011 .long __pabt_invalid @ b
1034 .long __und_invalid @ b
1044 *-----------------------------------------------------------------------------
1046 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1050 b vector_addrexcptn
1054 *-----------------------------------------------------------------------------
1073 .long __fiq_svc @ b
1083 W(b) vector_rst
1084 W(b) vector_und
1088 W(b) vector_pabt
1089 W(b) vector_dabt
1090 W(b) vector_addrexcptn
1091 W(b) vector_irq
1092 W(b) vector_fiq
1097 W(b) vector_rst
1098 W(b) vector_bhb_loop8_und
1102 W(b) vector_bhb_loop8_pabt
1103 W(b) vector_bhb_loop8_dabt
1104 W(b) vector_addrexcptn
1105 W(b) vector_bhb_loop8_irq
1106 W(b) vector_bhb_loop8_fiq
1110 W(b) vector_rst
1111 W(b) vector_bhb_bpiall_und
1115 W(b) vector_bhb_bpiall_pabt
1116 W(b) vector_bhb_bpiall_dabt
1117 W(b) vector_addrexcptn
1118 W(b) vector_bhb_bpiall_irq
1119 W(b) vector_bhb_bpiall_fiq