processor\-a\-side (full) in projects: linux-6.14.4

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/linux-6.14.4/Documentation/devicetree/bindings/interrupt-controller/
D	fsl,mu-msi.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Frank Li <[email protected]> 16 for one processor (A side) to signal the other processor (B side) using 20 different clocks (from each side of the different peripheral buses). 21 Therefore, the MU must synchronize the accesses from one side to the 23 registers (Processor A-side, Processor B-side). 28 - $ref: /schemas/interrupt-controller/msi-controller.yaml# [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/powerpc/power8/
D	frontend.json	5 …"BriefDescription": "Branch instruction completed with a target address less than current instruct… 41 "BriefDescription": "Cycles when a demand ifetch was pending", 47 "BriefDescription": "Number of I-ERAT reloads", 53 "BriefDescription": "IERAT Reloaded (Miss) for a 16M page", 60 "PublicDescription": "IERAT Reloaded (Miss) for a 4k page" 65 "BriefDescription": "IERAT Reloaded (Miss) for a 64k page", 89 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an… 90 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a… 95 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot… 96 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano… [all …]
D	other.json	11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to … 17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong … 83 …"BriefDescription": "Pairable BC+8 branch that has not been converted to a Resolve Finished in the… 89 …"BriefDescription": "Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipe… 113 …to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that re… 161 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d… 167 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d… 197 …ional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set thi… 203 …ional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set thi… 215 …anch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-for… [all …]
D	cache.json	5 …e processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a dif… 6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another … 11 …he processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a diff… 12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch… 17 …riefDescription": "The processor's data cache was reloaded from another chip's L4 on a different N… 18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen… 23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand … 24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o… 29 "BriefDescription": "Demand LD - L2 Miss (not L2 hit)", 35 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local … [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/powerpc/power9/
D	translation.json	5 "BriefDescription": "Processor cycles" 15 …BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core… 20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed" 25 …escription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same No… 35 …A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on th… 45 …"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipelin… 50 "BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)" 60 …A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a … 65 …"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (divisi… 70 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local … [all …]
D	marked.json	5 …"BriefDescription": "Number of cycles the marked instruction is experiencing a stall while it is n… 10 …"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond … 20 …Description": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's… 25 …riefDescription": "The processor's data cache was reloaded from another chip's memory on the same … 35 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with disp… 45 …"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's … 50 …"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's … 60 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due… 70 …iption": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO … 80 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without c… [all …]
D	pipeline.json	10 "BriefDescription": "Number of I-ERAT reloads" 15 …te that this count is per slice, so if a load spans multiple slices this event will increment mult… 25 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued… 30 …scription": "The processor's data cache was reloaded either shared or modified data from another c… 35 …ription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node o… 40 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl… 80 …ription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L… 90 …riefDescription": "The processor's data cache was reloaded from another chip's L4 on a different N… 95 …escription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core'… 100 …rbitration onto the issue pipe to another instruction (from the same thread or a different thread)" [all …]
D	other.json	30 "BriefDescription": "IERAT reloaded (after a miss) for 4K pages" 45 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local … 50 …cription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's … 55 …"BriefDescription": "A Conditional Branch that resolved to taken was mispredicted as not taken (du… 60 …"BriefDescription": "A demand load referenced a line in an active fuzzy prefetch stream. The strea… 65 "BriefDescription": "Read-write data cache collisions" 80 …"BriefDescription": "Cycles in which no new instructions can be dispatched to the ICT after a flus… 85 …"BriefDescription": "A radix translation attempt missed in the TLB and all levels of page walk cac… 90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core" 95 …"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory d… [all …]
D	cache.json	5 …ion": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set" 10 … allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks … 15 …"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (divisi… 20 …"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution p… 25 …n cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load" 35 …"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and… 40 …"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data… 45 …"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its … 50 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the … 55 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot… [all …]
/linux-6.14.4/Documentation/devicetree/bindings/mailbox/
D	fsl,mu.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dong Aisheng <[email protected]> 16 for one processor to signal the other processor using interrupts. 19 different clocks (from each side of the different peripheral buses). 20 Therefore, the MU must synchronize the accesses from one side to the 22 registers (Processor A-facing, Processor B-facing). 27 - const: fsl,imx6sx-mu 28 - const: fsl,imx7ulp-mu [all …]`
/linux-6.14.4/tools/perf/pmu-events/arch/x86/goldmontplus/
D	cache.json	7 …a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requ… 15 …a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to me… 20 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", 33 …a full or near full condition which likely indicates back pressure from the intra-die interconnect… 50 …"PublicDescription": "Counts memory requests originating from the core that reference a cache line… 61 … loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit… 72 …processor) in the system, one of those caching agents indicated that they had a dirty copy of the … 127 …that data was in the process of being brought into the L1 cache. Typically a load will receive th… 138 …"PublicDescription": "Counts the number of memory uops retired that is either a loads or a store o… 171 …ee the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memo… [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/goldmont/
D	cache.json	7 …a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requ… 15 …a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to me… 20 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", 33 …a full or near full condition which likely indicates back pressure from the intra-die interconnect… 50 …"PublicDescription": "Counts memory requests originating from the core that reference a cache line… 61 … loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit… 72 …processor) in the system, one of those caching agents indicated that they had a dirty copy of the … 127 …that data was in the process of being brought into the L1 cache. Typically a load will receive th… 138 …"PublicDescription": "Counts the number of memory uops retired that is either a loads or a store o… 171 …ee the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memo… [all …]
/linux-6.14.4/Documentation/devicetree/bindings/soc/qcom/
D	qcom,smp2p.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Andy Gross <[email protected]> 11 - Bjorn Andersson <[email protected]> 12 - Krzysztof Kozlowski <[email protected]> 16 of a single 32-bit value between two processors. Each value has a single 17 writer (the local side) and a single reader (the remote side). Values are 18 uniquely identified in the system by the directed edge (local processor ID to 19 remote processor ID) and a string identifier. [all …]
/linux-6.14.4/Documentation/admin-guide/hw-vuln/
D	spectre.rst	`1 .. SPDX-License-Identifier: GPL-2.0 3 Spectre Side Channels 6 Spectre is a class of side channel attacks that exploit branch prediction 8 bypassing access controls. Speculative execution side channel exploits 14 ------------------- 16 Speculative execution side channel methods affect a wide range of modern 22 - Intel Core, Atom, Pentium, and Xeon processors 24 - AMD Phenom, EPYC, and Zen processors 26 - IBM POWER and zSeries processors 28 - Higher end ARM processors [all …]`
D	gather_data_sampling.rst	1 .. SPDX-License-Identifier: GPL-2.0 3 GDS - Gather Data Sampling 6 Gather Data Sampling is a hardware vulnerability which allows unprivileged 10 ------- 11 When a gather instruction performs loads from memory, different data elements 12 are merged into the destination vector register. However, when a gather 13 instruction that is transiently executed encounters a fault, stale data from 15 destination vector register instead. This will allow a malicious attacker to 16 infer stale data using typical side channel techniques like cache timing 17 attacks. GDS is a purely sampling-based attack. [all …]
/linux-6.14.4/drivers/remoteproc/
D	omap_remoteproc.h	1 /* SPDX-License-Identifier: BSD-3-Clause / 3 Remote processor messaging 5 * Copyright (C) 2011-2020 Texas Instruments, Inc. 14 * enum - Predefined Mailbox Messages 21 * message waiting in its own receive-side vring. please note that currently 28 * @RP_MBOX_ECHO_REQUEST: a mailbox-level "ping" message. 30 * @RP_MBOX_ECHO_REPLY: a mailbox-level reply to a "ping" 32 * @RP_MBOX_ABORT_REQUEST: a "please crash" request, used for testing the 35 * @RP_MBOX_SUSPEND_AUTO: auto suspend request for the remote processor 37 * @RP_MBOX_SUSPEND_SYSTEM: system suspend request for the remote processor [all …]
/linux-6.14.4/arch/arm/kernel/
D	head-nommu.S	`1 /* SPDX-License-Identifier: GPL-2.0-only / 3 linux/arch/arm/kernel/head-nommu.S 5 * Copyright (C) 1994-2002 Russell King 6 * Copyright (C) 2003-2006 Hyok S. Choi 8 * Common kernel startup code (non-paged MM) 16 #include <asm/asm-offsets.h> 25 * --------------------------- 28 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 31 * See linux/arch/arm/tools/mach-types for the complete list of machine 46 THUMB( bx r9 ) @ If this is a Thumb-2 kernel, [all …]`
/linux-6.14.4/drivers/gpu/drm/imagination/
D	pvr_fw.h	1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT / 27 struct pvr_fw_object - container for firmware memory allocations 37 * @fw_mm_node: Node representing mapping in FW address space. @pvr_obj->lock must 63 * struct pvr_fw_defs - FW processor function table and static definitions 69 * FW processor specific initialisation. 73 * FW processor. 86 * FW processor specific finalisation. 118 * Map FW object into FW processor address space. 133 * Unmap FW object from FW processor address space. 187 * Those are processor dependent, and should be initialized by the [all …]
/linux-6.14.4/drivers/soc/qcom/
D	smp2p.c	1 // SPDX-License-Identifier: GPL-2.0-only 4 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. 26 * of a single 32-bit value between two processors. Each value has a single 27 * writer (the local side) and a single reader (the remote side). Values are 28 * uniquely identified in the system by the directed edge (local processor ID 29 * to remote processor ID) and a string identifier. 31 * Each processor is responsible for creating the outgoing SMEM items and each 32 * item is writable by the local processor and readable by the remote 33 * processor. By using two separate SMEM items that are single-reader and 34 * single-writer, SMP2P does not require any remote locking mechanisms. [all …]
/linux-6.14.4/drivers/irqchip/
D	irq-imx-mu-msi.c	1 // SPDX-License-Identifier: GPL-2.0-only 10 * Based on drivers/mailbox/imx-mailbox.c 27 #include "irq-msi-lib.h" 52 #define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) 53 #define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) 75 iowrite32(val, msi_data->regs + offs); in imx_mu_write() 80 return ioread32(msi_data->regs + offs); in imx_mu_read() 88 raw_spin_lock_irqsave(&msi_data->lock, flags); in imx_mu_xcr_rmw() 89 val = imx_mu_read(msi_data, msi_data->cfg->xCR[type]); in imx_mu_xcr_rmw() 92 imx_mu_write(msi_data, val, msi_data->cfg->xCR[type]); in imx_mu_xcr_rmw() [all …]
/linux-6.14.4/arch/s390/
D	Kconfig	`1 # SPDX-License-Identifier: GPL-2.0 65 Clang versions before 19.1.0 do not support A, 305 menu "Processor type and features" 335 prompt "Processor type" 341 depends on $(cc-option,-march=z10) 349 depends on $(cc-option,-march=z196) 358 depends on $(cc-option,-march=zEC12) 367 depends on $(cc-option,-march=z13) 376 depends on $(cc-option,-march=z14) 385 depends on $(cc-option,-march=z15) [all …]`
/linux-6.14.4/tools/perf/pmu-events/arch/x86/amdzen1/
D	memory.json	5 …"BriefDescription": "Bus lock when a locked operations crosses a cache boundary or is done on an u… 11 …n": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores.", 34 …increment represents an eight-byte access, although the instruction may only be accessing a portio… 39 "BriefDescription": "LS MAB allocates by type - DC prefetcher.", 45 "BriefDescription": "LS MAB allocates by type - stores.", 51 "BriefDescription": "LS MAB allocates by type - loads.", 63 "BriefDescription": "L1 DTLB Miss of a page of 1G size.", 69 "BriefDescription": "L1 DTLB Miss of a page of 2M size.", 75 "BriefDescription": "L1 DTLB Miss of a page of 32K size.", 81 "BriefDescription": "L1 DTLB Miss of a page of 4K size.", [all …]
/linux-6.14.4/Documentation/devicetree/bindings/arm/
D	arm,coresight-dummy-sink.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/arm/arm,coresight-dummy-sink.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 specification and can be connected in various topologies to suit a particular 19 Qualcomm platforms. It is a mini-USB hub implemented to support the USB-based 20 debug and trace capabilities. For this device, a dummy driver is needed to 21 register it as Coresight sink device in kernel side, so that path can be 23 coresight link of AP processor. It provides Coresight API for operations on 28 side for dummy sink component. [all …]
D	arm,coresight-dummy-source.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/arm/arm,coresight-dummy-source.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 specification and can be connected in various topologies to suit a particular 19 there would be Coresight source trace components on sub-processor which 20 are connected to AP processor via debug bus. For these devices, a dummy driver 27 side for dummy source component. 30 - Mike Leach <[email protected]> 31 - Suzuki K Poulose <[email protected]> [all …]
/linux-6.14.4/Documentation/hid/
D	intel-ish-hid.rst	5 A sensor hub enables the ability to offload sensor polling and algorithm 6 processing to a dedicated low power co-processor. This allows the core 7 processor to go into low power modes more often, resulting in increased 11 Sensor usage tables. These may be found in tablets, 2-in-1 convertible laptops 14 Intel® introduced integrated sensor hubs as a part of the SoC starting from 24 Using a analogy with a usbhid implementation, the ISH follows a similar model 25 for a very high speed communication:: 27 ----------------- ---------------------- 28 \| USB HID \| --> \| ISH HID \| 29 ----------------- ---------------------- [all …]

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