Lines Matching +full:processor +full:- +full:a +full:- +full:side

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Frank Li <[email protected]>
16   for one processor (A side) to signal the other processor (B side) using
20   different clocks (from each side of the different peripheral buses).
21   Therefore, the MU must synchronize the accesses from one side to the
23   registers (Processor A-side, Processor B-side).
28   - $ref: /schemas/interrupt-controller/msi-controller.yaml#
33       - fsl,imx6sx-mu-msi
34       - fsl,imx7ulp-mu-msi
35       - fsl,imx8ulp-mu-msi
36       - fsl,imx8ulp-mu-msi-s4
40       - description: a side register base address
41       - description: b side register base address
43   reg-names:
45       - const: processor-a-side
46       - const: processor-b-side
49     description: a side interrupt number.
55   power-domains:
57       - description: a side power domain
58       - description: b side power domain
60   power-domain-names:
62       - const: processor-a-side
63       - const: processor-b-side
65   msi-controller: true
67   "#msi-cells":
71   - compatible
72   - reg
73   - interrupts
74   - msi-controller
75   - "#msi-cells"
80   - |
81     #include <dt-bindings/interrupt-controller/arm-gic.h>
82     #include <dt-bindings/firmware/imx/rsrc.h>
84     msi-controller@5d270000 {
85         compatible = "fsl,imx6sx-mu-msi";
86         msi-controller;
87         #msi-cells = <0>;
88         reg = <0x5d270000 0x10000>,     /* A side */
89               <0x5d300000 0x10000>;     /* B side */
90         reg-names = "processor-a-side", "processor-b-side";
92         power-domains = <&pd IMX_SC_R_MU_12A>,
94         power-domain-names = "processor-a-side", "processor-b-side";