Lines Matching +full:processor +full:- +full:a +full:- +full:side

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Dong Aisheng <[email protected]>
16   for one processor to signal the other processor using interrupts.
19   different clocks (from each side of the different peripheral buses).
20   Therefore, the MU must synchronize the accesses from one side to the
22   registers (Processor A-facing, Processor B-facing).
27       - const: fsl,imx6sx-mu
28       - const: fsl,imx7ulp-mu
29       - const: fsl,imx8ulp-mu
30       - const: fsl,imx8-mu-scu
31       - const: fsl,imx8-mu-seco
32       - const: fsl,imx8ulp-mu-s4
33       - const: fsl,imx93-mu-s4
34       - const: fsl,imx95-mu
35       - const: fsl,imx95-mu-ele
36       - const: fsl,imx95-mu-v2x
37       - items:
38           - const: fsl,imx93-mu
39           - const: fsl,imx8ulp-mu
40       - items:
41           - enum:
42               - fsl,imx7s-mu
43               - fsl,imx8mq-mu
44               - fsl,imx8mm-mu
45               - fsl,imx8mn-mu
46               - fsl,imx8mp-mu
47               - fsl,imx8qm-mu
48               - fsl,imx8qxp-mu
49           - const: fsl,imx6sx-mu
50       - description: To communicate with i.MX8 SCU with fast IPC
52           - const: fsl,imx8-mu-scu
53           - enum:
54               - fsl,imx8qm-mu
55               - fsl,imx8qxp-mu
56           - const: fsl,imx6sx-mu
65   interrupt-names:
68       - const: tx
69       - const: rx
71   "#mbox-cells":
80       A total of 21 channels.  Following types are
82       0 - TX channel with 32bit transmit register and IRQ transmit
84       1 - RX channel with 32bit receive register and IRQ support
85       2 - TX doorbell channel. Without own register and no ACK support.
86       3 - RX doorbell channel.
87       4 - RST channel
88       5 - Tx doorbell channel. With S/W ACK from the other side.
94   fsl,mu-side-b:
95     description: boolean, if present, means it is for side B MU.
98   power-domains:
103   '#address-cells':
106   '#size-cells':
110   "^sram@[a-f0-9]+":
115   - compatible
116   - reg
117   - interrupts
118   - "#mbox-cells"
121   - if:
125             - fsl,imx93-mu-s4
128         interrupt-names:
139           - interrupt-names
141   - if:
145             const: fsl,imx95-mu
148         "^sram@[a-f0-9]+": false
153   - |
154     #include <dt-bindings/interrupt-controller/arm-gic.h>
157         compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
160         #mbox-cells = <2>;
163   - |
164     #include <dt-bindings/interrupt-controller/arm-gic.h>
167         compatible = "fsl,imx95-mu";
171         #address-cells = <1>;
172         #size-cells = <1>;
173         #mbox-cells = <2>;
176             compatible = "mmio-sram";
179             #address-cells = <1>;
180             #size-cells = <1>;
182             scmi-sram-section@0 {
183                 compatible = "arm,scmi-shmem";
187             scmi-sram-section@80 {
188                 compatible = "arm,scmi-shmem";