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/aosp_15_r20/external/mesa3d/src/gallium/drivers/nouveau/nvc0/
H A Dnvc0_context.c27 #include "nvc0/nvc0_context.h"
28 #include "nvc0/nvc0_screen.h"
29 #include "nvc0/nvc0_resource.h"
41 struct nvc0_context *nvc0 = nvc0_context(pipe); in nvc0_svm_migrate() local
42 struct nouveau_screen *screen = &nvc0->screen->base; in nvc0_svm_migrate()
83 struct nvc0_context *nvc0 = nvc0_context(pipe); in nvc0_flush() local
86 nouveau_fence_ref(nvc0->base.fence, (struct nouveau_fence **)fence); in nvc0_flush()
88 PUSH_KICK(nvc0->base.pushbuf); /* fencing handled in kick_notify */ in nvc0_flush()
90 nouveau_context_update_frame_stats(&nvc0->base); in nvc0_flush()
105 struct nvc0_context *nvc0 = nvc0_context(pipe); in nvc0_memory_barrier() local
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H A Dnvc0_state_validate.c6 #include "nvc0/nvc0_context.h"
38 gm200_validate_sample_locations(struct nvc0_context *nvc0, unsigned ms) in gm200_validate_sample_locations() argument
40 struct nouveau_pushbuf *push = nvc0->base.pushbuf; in gm200_validate_sample_locations()
41 struct nvc0_screen *screen = nvc0->screen; in gm200_validate_sample_locations()
55 if (nvc0->sample_locations_enabled) { in gm200_validate_sample_locations()
57 memcpy(locations, nvc0->sample_locations, sizeof(locations)); in gm200_validate_sample_locations()
59 &screen->base.base, nvc0->framebuffer.height, ms, locations); in gm200_validate_sample_locations()
112 nvc0_validate_sample_locations(struct nvc0_context *nvc0, unsigned ms) in nvc0_validate_sample_locations() argument
114 struct nouveau_pushbuf *push = nvc0->base.pushbuf; in nvc0_validate_sample_locations()
115 struct nvc0_screen *screen = nvc0->screen; in nvc0_validate_sample_locations()
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H A Dnvc0_vbo.c32 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nvc0_query_hw.h"
34 #include "nvc0/nvc0_resource.h"
36 #include "nvc0/nvc0_3d.xml.h"
54 struct nvc0_context *nvc0 = nvc0_context(pipe); in nvc0_vertex_state_create() local
119 if (!ve->src_stride && nvc0->screen->eng3d->oclass < GM107_3D_CLASS) in nvc0_vertex_state_create()
177 nvc0_set_constant_vertex_attrib(struct nvc0_context *nvc0, const unsigned a) in nvc0_set_constant_vertex_attrib() argument
179 struct nouveau_pushbuf *push = nvc0->base.pushbuf; in nvc0_set_constant_vertex_attrib()
180 struct pipe_vertex_element *ve = &nvc0->vertex->element[a].pipe; in nvc0_set_constant_vertex_attrib()
181 struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[ve->vertex_buffer_index]; in nvc0_set_constant_vertex_attrib()
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H A Dnvc0_state.c33 #include "nvc0/nvc0_stateobj.h"
34 #include "nvc0/nvc0_context.h"
35 #include "nvc0/nvc0_query_hw.h"
37 #include "nvc0/nvc0_3d.xml.h"
198 struct nvc0_context *nvc0 = nvc0_context(pipe); in nvc0_blend_state_bind() local
200 nvc0->blend = hwcso; in nvc0_blend_state_bind()
201 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND; in nvc0_blend_state_bind()
350 struct nvc0_context *nvc0 = nvc0_context(pipe); in nvc0_rasterizer_state_bind() local
352 nvc0->rast = hwcso; in nvc0_rasterizer_state_bind()
353 nvc0->dirty_3d |= NVC0_NEW_3D_RASTERIZER; in nvc0_rasterizer_state_bind()
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H A Dnvc0_shader_state.c28 #include "nvc0/nvc0_context.h"
29 #include "nvc0/nvc0_query_hw.h"
31 #include "nvc0/nvc0_compute.xml.h"
34 nvc0_program_update_context_state(struct nvc0_context *nvc0, in nvc0_program_update_context_state() argument
38 const uint32_t flags = NV_VRAM_DOMAIN(&nvc0->screen->base) | NOUVEAU_BO_RDWR; in nvc0_program_update_context_state()
39 if (!nvc0->state.tls_required) in nvc0_program_update_context_state()
40 BCTX_REFN_bo(nvc0->bufctx_3d, 3D_TLS, flags, nvc0->screen->tls); in nvc0_program_update_context_state()
41 nvc0->state.tls_required |= 1 << stage; in nvc0_program_update_context_state()
43 if (nvc0->state.tls_required == (1 << stage)) in nvc0_program_update_context_state()
44 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TLS); in nvc0_program_update_context_state()
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H A Dnvc0_surface.c39 #include "nvc0/nvc0_context.h"
40 #include "nvc0/nvc0_resource.h"
214 struct nvc0_context *nvc0 = nvc0_context(pipe); in nvc0_resource_copy_region() local
220 nouveau_copy_buffer(&nvc0->base, in nvc0_resource_copy_region()
223 NOUVEAU_DRV_STAT(&nvc0->screen->base, buf_copy_bytes, src_box->width); in nvc0_resource_copy_region()
226 NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_copy_count, 1); in nvc0_resource_copy_region()
252 nvc0->m2mf_copy_rect(nvc0, &drect, &srect, nx, ny); in nvc0_resource_copy_region()
270 BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(src), RD); in nvc0_resource_copy_region()
271 BCTX_REFN(nvc0->bufctx, 2D, nv04_resource(dst), WR); in nvc0_resource_copy_region()
272 nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx); in nvc0_resource_copy_region()
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H A Dnvc0_tex.c23 #include "nvc0/nvc0_context.h"
24 #include "nvc0/nvc0_resource.h"
25 #include "nvc0/gm107_texture.xml.h"
26 #include "nvc0/nvc0_compute.xml.h"
453 nvc0_update_tic(struct nvc0_context *nvc0, struct nv50_tic_entry *tic, in nvc0_update_tic() argument
469 nvc0->base.push_data(&nvc0->base, nvc0->screen->txc, tic->id * 32, in nvc0_update_tic()
470 NV_VRAM_DOMAIN(&nvc0->screen->base), 32, in nvc0_update_tic()
479 nvc0_validate_tic(struct nvc0_context *nvc0, int s) in nvc0_validate_tic() argument
482 struct nouveau_pushbuf *push = nvc0->base.pushbuf; in nvc0_validate_tic()
487 for (i = 0; i < nvc0->num_textures[s]; ++i) { in nvc0_validate_tic()
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H A Dnvc0_compute.c25 #include "nvc0/nvc0_context.h"
27 #include "nvc0/nvc0_compute.xml.h"
121 nvc0_compute_validate_samplers(struct nvc0_context *nvc0) in nvc0_compute_validate_samplers() argument
123 bool need_flush = nvc0_validate_tsc(nvc0, 5); in nvc0_compute_validate_samplers()
125 BEGIN_NVC0(nvc0->base.pushbuf, NVC0_CP(TSC_FLUSH), 1); in nvc0_compute_validate_samplers()
126 PUSH_DATA (nvc0->base.pushbuf, 0); in nvc0_compute_validate_samplers()
131 nvc0->samplers_dirty[s] = ~0; in nvc0_compute_validate_samplers()
132 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLERS; in nvc0_compute_validate_samplers()
136 nvc0_compute_validate_textures(struct nvc0_context *nvc0) in nvc0_compute_validate_textures() argument
138 bool need_flush = nvc0_validate_tic(nvc0, 5); in nvc0_compute_validate_textures()
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H A Dnve4_compute.c25 #include "nvc0/nvc0_context.h"
26 #include "nvc0/nve4_compute.h"
181 gm107_compute_validate_surfaces(struct nvc0_context *nvc0, in gm107_compute_validate_surfaces() argument
185 struct nouveau_pushbuf *push = nvc0->base.pushbuf; in gm107_compute_validate_surfaces()
186 struct nvc0_screen *screen = nvc0->screen; in gm107_compute_validate_surfaces()
187 struct nouveau_bo *txc = nvc0->screen->txc; in gm107_compute_validate_surfaces()
192 tic = nv50_tic_entry(nvc0->images_tic[s][slot]); in gm107_compute_validate_surfaces()
195 nvc0_update_tic(nvc0, tic, res); in gm107_compute_validate_surfaces()
198 tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic); in gm107_compute_validate_surfaces()
219 nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32); in gm107_compute_validate_surfaces()
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H A Dnvc0_vbo_translate.c8 #include "nvc0/nvc0_context.h"
9 #include "nvc0/nvc0_resource.h"
11 #include "nvc0/nvc0_3d.xml.h"
43 nvc0_push_context_init(struct nvc0_context *nvc0, struct push_context *ctx) in nvc0_push_context_init() argument
45 ctx->push = nvc0->base.pushbuf; in nvc0_push_context_init()
47 ctx->translate = nvc0->vertex->translate; in nvc0_push_context_init()
48 ctx->vertex_size = nvc0->vertex->size; in nvc0_push_context_init()
52 nvc0->vertprog->vp.need_vertex_id && (nvc0->vertex->num_elements < 32); in nvc0_push_context_init()
55 ctx->edgeflag.enabled = nvc0->vertprog->vp.edgeflag < PIPE_MAX_ATTRIBS; in nvc0_push_context_init()
64 nvc0_vertex_configure_translate(struct nvc0_context *nvc0, int32_t index_bias) in nvc0_vertex_configure_translate() argument
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H A Dnvc0_query_hw.c26 #include "nvc0/nvc0_context.h"
27 #include "nvc0/nvc0_query_hw.h"
28 #include "nvc0/nvc0_query_hw_metric.h"
29 #include "nvc0/nvc0_query_hw_sm.h"
34 nvc0_hw_query_allocate(struct nvc0_context *nvc0, struct nvc0_query *q, in nvc0_hw_query_allocate() argument
38 struct nvc0_screen *screen = nvc0->screen; in nvc0_hw_query_allocate()
47 nouveau_fence_work(nvc0->base.fence, in nvc0_hw_query_allocate()
58 ret = BO_MAP(&screen->base, hq->bo, 0, nvc0->base.client); in nvc0_hw_query_allocate()
60 nvc0_hw_query_allocate(nvc0, q, 0); in nvc0_hw_query_allocate()
86 nvc0_hw_query_rotate(struct nvc0_context *nvc0, struct nvc0_query *q) in nvc0_hw_query_rotate() argument
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H A Dnvc0_transfer.c4 #include "nvc0/nvc0_context.h"
15 nvc0_m2mf_transfer_rect(struct nvc0_context *nvc0, in nvc0_m2mf_transfer_rect() argument
20 struct nouveau_pushbuf *push = nvc0->base.pushbuf; in nvc0_m2mf_transfer_rect()
21 struct nouveau_bufctx *bctx = nvc0->bufctx; in nvc0_m2mf_transfer_rect()
110 nve4_m2mf_transfer_rect(struct nvc0_context *nvc0, in nve4_m2mf_transfer_rect() argument
129 struct nouveau_pushbuf *push = nvc0->base.pushbuf; in nve4_m2mf_transfer_rect()
130 struct nouveau_bufctx *bctx = nvc0->bufctx; in nve4_m2mf_transfer_rect()
203 struct nvc0_context *nvc0 = nvc0_context(&nv->pipe); in nvc0_m2mf_push_linear() local
208 nouveau_bufctx_refn(nvc0->bufctx, 0, dst, domain | NOUVEAU_BO_WR); in nvc0_m2mf_push_linear()
209 nouveau_pushbuf_bufctx(push, nvc0->bufctx); in nvc0_m2mf_push_linear()
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H A Dnvc0_program.c30 #include "nvc0/nvc0_context.h"
33 #include "nvc0/nve4_compute.h"
761 nvc0_program_alloc_code(struct nvc0_context *nvc0, struct nvc0_program *prog) in nvc0_program_alloc_code() argument
763 struct nvc0_screen *screen = nvc0->screen; in nvc0_program_alloc_code()
813 nvc0_program_upload_code(struct nvc0_context *nvc0, struct nvc0_program *prog) in nvc0_program_upload_code() argument
815 struct nvc0_screen *screen = nvc0->screen; in nvc0_program_upload_code()
852 nvc0->base.push_data(&nvc0->base, screen->text, prog->code_base, in nvc0_program_upload_code()
855 nvc0->base.push_data(&nvc0->base, screen->text, code_pos, in nvc0_program_upload_code()
861 nvc0_program_upload(struct nvc0_context *nvc0, struct nvc0_program *prog) in nvc0_program_upload() argument
863 struct nvc0_screen *screen = nvc0->screen; in nvc0_program_upload()
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H A Dnvc0_query.c27 #include "nvc0/nvc0_context.h"
28 #include "nvc0/nvc0_query.h"
29 #include "nvc0/nvc0_query_sw.h"
30 #include "nvc0/nvc0_query_hw.h"
31 #include "nvc0/nvc0_query_hw_metric.h"
32 #include "nvc0/nvc0_query_hw_sm.h"
37 struct nvc0_context *nvc0 = nvc0_context(pipe); in nvc0_create_query() local
40 q = nvc0_sw_create_query(nvc0, type, index); in nvc0_create_query()
42 q = nvc0_hw_create_query(nvc0, type, index); in nvc0_create_query()
100 struct nvc0_context *nvc0 = nvc0_context(pipe); in nvc0_render_condition() local
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H A Dnvc0_context.h14 #include "nvc0/nvc0_winsys.h"
15 #include "nvc0/nvc0_stateobj.h"
16 #include "nvc0/nvc0_screen.h"
17 #include "nvc0/nvc0_program.h"
18 #include "nvc0/nvc0_resource.h"
19 #include "nvc0/nvc0_query.h"
27 #include "nvc0/nvc0_3d.xml.h"
29 #include "nvc0/nvc0_m2mf.xml.h"
30 #include "nvc0/nve4_copy.xml.h"
31 #include "nvc0/nve4_p2mf.xml.h"
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H A Dnvc0_query_hw_sm.c26 #include "nvc0/nvc0_context.h"
27 #include "nvc0/nvc0_query_hw_sm.h"
30 #include "nvc0/nve4_compute.xml.h"
31 #include "nvc0/nvc0_compute.xml.h"
600 uint32_t src_mask; /* mask for signal selection (only for NVC0:NVE4) */
1744 /* === PERFORMANCE MONITORING COUNTERS for NVC0:NVE4 === */
2282 nvc0_hw_sm_query_get_cfg(struct nvc0_context *nvc0, struct nvc0_hw_query *hq) in nvc0_hw_sm_query_get_cfg() argument
2285 struct nvc0_screen *screen = nvc0->screen; in nvc0_hw_sm_query_get_cfg()
2302 nvc0_hw_sm_destroy_query(struct nvc0_context *nvc0, struct nvc0_hw_query *hq) in nvc0_hw_sm_destroy_query() argument
2305 nvc0_hw_query_allocate(nvc0, q, 0); in nvc0_hw_sm_destroy_query()
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H A Dnvc0_query_hw_metric.c23 #include "nvc0/nvc0_context.h"
24 #include "nvc0/nvc0_query_hw_metric.h"
25 #include "nvc0/nvc0_query_hw_sm.h"
445 nvc0_hw_metric_query_get_cfg(struct nvc0_context *nvc0, struct nvc0_hw_query *hq) in nvc0_hw_metric_query_get_cfg() argument
448 struct nvc0_screen *screen = nvc0->screen; in nvc0_hw_metric_query_get_cfg()
465 nvc0_hw_metric_destroy_query(struct nvc0_context *nvc0, in nvc0_hw_metric_destroy_query() argument
473 hmq->queries[i]->funcs->destroy_query(nvc0, hmq->queries[i]); in nvc0_hw_metric_destroy_query()
478 nvc0_hw_metric_begin_query(struct nvc0_context *nvc0, struct nvc0_hw_query *hq) in nvc0_hw_metric_begin_query() argument
485 ret = hmq->queries[i]->funcs->begin_query(nvc0, hmq->queries[i]); in nvc0_hw_metric_begin_query()
493 nvc0_hw_metric_end_query(struct nvc0_context *nvc0, struct nvc0_hw_query *hq) in nvc0_hw_metric_end_query() argument
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H A Dnvc0_miptree.c31 #include "nvc0/nvc0_context.h"
32 #include "nvc0/nvc0_resource.h"
327 if (config->nvc0.memtype == 0x00) in nvc0_miptree_get_modifier()
329 if (NVC0_TILE_MODE_Y(config->nvc0.tile_mode) > 5) in nvc0_miptree_get_modifier()
331 if (config->nvc0.memtype != uc_kind) in nvc0_miptree_get_modifier()
338 config->nvc0.memtype, in nvc0_miptree_get_modifier()
339 NVC0_TILE_MODE_Y(config->nvc0.tile_mode)); in nvc0_miptree_get_modifier()
496 bo_config.nvc0.memtype = 0; in nvc0_miptree_create()
498 bo_config.nvc0.memtype = (modifier >> 12) & 0xff; in nvc0_miptree_create()
501 bo_config.nvc0.memtype = nvc0_mt_choose_storage_type(pscreen, mt, compressed); in nvc0_miptree_create()
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/aosp_15_r20/external/mesa3d/src/gallium/drivers/nouveau/
H A Dmeson.build108 'nvc0/cla0c0qmd.h',
109 'nvc0/clc0c0qmd.h',
110 'nvc0/clc3c0qmd.h',
111 'nvc0/drf.h',
112 'nvc0/qmd.h',
113 'nvc0/qmda0c0.c',
114 'nvc0/qmdc0c0.c',
115 'nvc0/qmdc3c0.c',
116 'nvc0/gm107_texture.xml.h',
117 'nvc0/nvc0_3d.xml.h',
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/aosp_15_r20/external/mesa3d/docs/
H A Dfeatures.txt39 GL 3.0, GLSL 1.30 --- all DONE: freedreno, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, virgl, z…
72 GL 3.1, GLSL 1.40 --- all DONE: freedreno, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, virgl, z…
85 GL 3.2, GLSL 1.50 --- all DONE: freedreno, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, virgl, z…
100 GL 3.3, GLSL 3.30 --- all DONE: freedreno, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, virgl, z…
114 GL 4.0, GLSL 4.00 --- all DONE: freedreno/a6xx, nvc0, r600, radeonsi, llvmpipe, virgl, zink, d3d12,…
143 GL 4.1, GLSL 4.10 --- all DONE: freedreno/a6xx, nvc0, r600, radeonsi, llvmpipe, virgl, zink, d3d12,…
153 GL 4.2, GLSL 4.20 -- all DONE: freedreno/a6xx, nvc0, r600, radeonsi, llvmpipe, virgl, zink, d3d12, …
169 GL 4.3, GLSL 4.30 -- all DONE: freedreno/a6xx, nvc0, r600, radeonsi, llvmpipe, virgl, zink, d3d12, …
195 GL 4.4, GLSL 4.40 -- all DONE: freedreno/a6xx, nvc0, r600, radeonsi, llvmpipe, virgl, zink, iris, c…
213 GL 4.5, GLSL 4.50 -- all DONE: freedreno/a6xx, nvc0, r600, radeonsi, llvmpipe, virgl, zink, iris, c…
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/aosp_15_r20/external/mesa3d/docs/relnotes/
H A D10.3.rst29 - GL_ARB_ES3_compatibility on nv50, nvc0, r600, radeonsi, softpipe,
33 - GL_ARB_conditional_render_inverted on i965, nvc0, softpipe, llvmpipe
34 - GL_ARB_derivative_control on i965, nv50, nvc0, r600
35 - GL_ARB_draw_indirect on nvc0, radeonsi
37 - GL_ARB_fragment_layer_viewport on nv50, nvc0, llvmpipe, r600
38 - GL_ARB_gpu_shader5 on i965/gen7, nvc0
39 - GL_ARB_multi_draw_indirect on nvc0, radeonsi
41 - GL_ARB_seamless_cubemap_per_texture on i965, llvmpipe, nvc0, r600,
43 - GL_ARB_stencil_texturing on nv50, nvc0, r600, and radeonsi
44 - GL_ARB_texture_barrier on nv50, nvc0, r300, r600, radeonsi
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H A D12.0.0.rst28 - OpenGL 4.3 on nvc0, radeonsi, i965 (Gen8+)
29 - OpenGL ES 3.1 on nvc0, radeonsi
30 - GL_ARB_ES3_1_compatibility on nvc0, radeonsi
31 - GL_ARB_compute_shader on nvc0, radeonsi, softpipe
32 - GL_ARB_cull_distance on i965/gen6+, nv50, nvc0, llvmpipe, softpipe
33 - GL_ARB_framebuffer_no_attachments on nvc0, r600, radeonsi, softpipe
36 - GL_ARB_robust_buffer_access_behavior on i965, nvc0, radeonsi
38 - GL_ARB_shader_atomic_counter_ops on nvc0, radeonsi, softpipe
39 - GL_ARB_shader_image_load_store on nvc0, radeonsi, softpipe
40 - GL_ARB_shader_image_size on nvc0, radeonsi, softpipe
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H A D11.1.3.rst148 - nvc0/ir: fix converting between predicate and gpr
149 - nvc0: add some missing PUSH_SPACE's
150 - nvc0: avoid negatives in PUSH_SPACE argument
159 - nv50,nvc0: bump minimum texture buffer offset alignment
160 - nvc0: reset TFB bufctx when we no longer hold a reference to the
163 - nvc0: fix blit triangle size to fully cover FB's > 8192x8192
168 - nv50/ir: fix indirect texturing for non-array textures on nvc0
169 - nvc0/ir: fix picking of coordinates from tex instruction for
171 - nvc0: disable primitive restart and index bias during blits
261 - nvc0: make sure to delete samplers used by compute shaders
H A D11.1.1.rst92 - nvc0: don't forget to reset VTX_TMP bufctx slot after blit completion
94 - nv50,nvc0: make sure there's pushbuf space and that we ref the bo
96 - nv50,nvc0: fix crash when increasing bsp bo size for h264
97 - nvc0: scale up inter_bo size so that it's 16M for a 4K video
109 - nvc0: Set winding order regardless of domain.
151 - nv50,nvc0: fix use-after-free when vertex buffers are unbound
161 - nvc0: free memory allocated by the prog which reads MP perf counters
162 - nv50,nvc0: free memory allocated by performance metrics
/aosp_15_r20/external/libdrm/nouveau/
H A Dabi16.c63 struct nvc0_fifo *nvc0 = obj->data; in abi16_chan_nvc0() local
71 nvc0->base.channel = req.channel; in abi16_chan_nvc0()
72 nvc0->base.pushbuf = req.pushbuf_domains; in abi16_chan_nvc0()
73 nvc0->notify = req.notifier_handle; in abi16_chan_nvc0()
74 nvc0->base.object->handle = req.channel; in abi16_chan_nvc0()
75 nvc0->base.object->length = sizeof(*nvc0); in abi16_chan_nvc0()
293 bo->config.nvc0.memtype = (info->tile_flags & 0xff00) >> 8; in abi16_bo_info()
294 bo->config.nvc0.tile_mode = info->tile_mode; in abi16_bo_info()
338 info->tile_flags = (config->nvc0.memtype & 0xff) << 8; in abi16_bo_init()
339 info->tile_mode = config->nvc0.tile_mode; in abi16_bo_init()

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