1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "pipe/p_defines.h"
24 #include "util/u_framebuffer.h"
25 #include "util/u_helpers.h"
26 #include "util/u_inlines.h"
27 #include "util/u_transfer.h"
28
29 #include "compiler/nir/nir.h"
30 #include "compiler/nir/nir_serialize.h"
31 #include "nir/tgsi_to_nir.h"
32
33 #include "nvc0/nvc0_stateobj.h"
34 #include "nvc0/nvc0_context.h"
35 #include "nvc0/nvc0_query_hw.h"
36
37 #include "nvc0/nvc0_3d.xml.h"
38
39 #include "nouveau_gldefs.h"
40
41 static inline uint32_t
nvc0_colormask(unsigned mask)42 nvc0_colormask(unsigned mask)
43 {
44 uint32_t ret = 0;
45
46 if (mask & PIPE_MASK_R)
47 ret |= 0x0001;
48 if (mask & PIPE_MASK_G)
49 ret |= 0x0010;
50 if (mask & PIPE_MASK_B)
51 ret |= 0x0100;
52 if (mask & PIPE_MASK_A)
53 ret |= 0x1000;
54
55 return ret;
56 }
57
58 #define NVC0_BLEND_FACTOR_CASE(a, b) \
59 case PIPE_BLENDFACTOR_##a: return NV50_BLEND_FACTOR_##b
60
61 static inline uint32_t
nvc0_blend_fac(unsigned factor)62 nvc0_blend_fac(unsigned factor)
63 {
64 switch (factor) {
65 NVC0_BLEND_FACTOR_CASE(ONE, ONE);
66 NVC0_BLEND_FACTOR_CASE(SRC_COLOR, SRC_COLOR);
67 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA, SRC_ALPHA);
68 NVC0_BLEND_FACTOR_CASE(DST_ALPHA, DST_ALPHA);
69 NVC0_BLEND_FACTOR_CASE(DST_COLOR, DST_COLOR);
70 NVC0_BLEND_FACTOR_CASE(SRC_ALPHA_SATURATE, SRC_ALPHA_SATURATE);
71 NVC0_BLEND_FACTOR_CASE(CONST_COLOR, CONSTANT_COLOR);
72 NVC0_BLEND_FACTOR_CASE(CONST_ALPHA, CONSTANT_ALPHA);
73 NVC0_BLEND_FACTOR_CASE(SRC1_COLOR, SRC1_COLOR);
74 NVC0_BLEND_FACTOR_CASE(SRC1_ALPHA, SRC1_ALPHA);
75 NVC0_BLEND_FACTOR_CASE(ZERO, ZERO);
76 NVC0_BLEND_FACTOR_CASE(INV_SRC_COLOR, ONE_MINUS_SRC_COLOR);
77 NVC0_BLEND_FACTOR_CASE(INV_SRC_ALPHA, ONE_MINUS_SRC_ALPHA);
78 NVC0_BLEND_FACTOR_CASE(INV_DST_ALPHA, ONE_MINUS_DST_ALPHA);
79 NVC0_BLEND_FACTOR_CASE(INV_DST_COLOR, ONE_MINUS_DST_COLOR);
80 NVC0_BLEND_FACTOR_CASE(INV_CONST_COLOR, ONE_MINUS_CONSTANT_COLOR);
81 NVC0_BLEND_FACTOR_CASE(INV_CONST_ALPHA, ONE_MINUS_CONSTANT_ALPHA);
82 NVC0_BLEND_FACTOR_CASE(INV_SRC1_COLOR, ONE_MINUS_SRC1_COLOR);
83 NVC0_BLEND_FACTOR_CASE(INV_SRC1_ALPHA, ONE_MINUS_SRC1_ALPHA);
84 default:
85 return NV50_BLEND_FACTOR_ZERO;
86 }
87 }
88
89 static void *
nvc0_blend_state_create(struct pipe_context * pipe,const struct pipe_blend_state * cso)90 nvc0_blend_state_create(struct pipe_context *pipe,
91 const struct pipe_blend_state *cso)
92 {
93 struct nvc0_blend_stateobj *so = CALLOC_STRUCT(nvc0_blend_stateobj);
94 int i;
95 int r; /* reference */
96 uint32_t ms;
97 uint8_t blend_en = 0;
98 bool indep_masks = false;
99 bool indep_funcs = false;
100
101 so->pipe = *cso;
102
103 /* check which states actually have differing values */
104 if (cso->independent_blend_enable) {
105 for (r = 0; r < 8 && !cso->rt[r].blend_enable; ++r);
106 blend_en |= 1 << r;
107 for (i = r + 1; i < 8; ++i) {
108 if (!cso->rt[i].blend_enable)
109 continue;
110 blend_en |= 1 << i;
111 if (cso->rt[i].rgb_func != cso->rt[r].rgb_func ||
112 cso->rt[i].rgb_src_factor != cso->rt[r].rgb_src_factor ||
113 cso->rt[i].rgb_dst_factor != cso->rt[r].rgb_dst_factor ||
114 cso->rt[i].alpha_func != cso->rt[r].alpha_func ||
115 cso->rt[i].alpha_src_factor != cso->rt[r].alpha_src_factor ||
116 cso->rt[i].alpha_dst_factor != cso->rt[r].alpha_dst_factor) {
117 indep_funcs = true;
118 break;
119 }
120 }
121 for (; i < 8; ++i)
122 blend_en |= (cso->rt[i].blend_enable ? 1 : 0) << i;
123
124 for (i = 1; i < 8; ++i) {
125 if (cso->rt[i].colormask != cso->rt[0].colormask) {
126 indep_masks = true;
127 break;
128 }
129 }
130 } else {
131 r = 0;
132 if (cso->rt[0].blend_enable)
133 blend_en = 0xff;
134 }
135
136 if (cso->logicop_enable) {
137 SB_BEGIN_3D(so, LOGIC_OP_ENABLE, 2);
138 SB_DATA (so, 1);
139 SB_DATA (so, nvgl_logicop_func(cso->logicop_func));
140
141 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, 0);
142 } else {
143 SB_IMMED_3D(so, LOGIC_OP_ENABLE, 0);
144
145 SB_IMMED_3D(so, BLEND_INDEPENDENT, indep_funcs);
146 SB_IMMED_3D(so, MACRO_BLEND_ENABLES, blend_en);
147 if (indep_funcs) {
148 for (i = 0; i < 8; ++i) {
149 if (cso->rt[i].blend_enable) {
150 SB_BEGIN_3D(so, IBLEND_EQUATION_RGB(i), 6);
151 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].rgb_func));
152 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_src_factor));
153 SB_DATA (so, nvc0_blend_fac(cso->rt[i].rgb_dst_factor));
154 SB_DATA (so, nvgl_blend_eqn(cso->rt[i].alpha_func));
155 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_src_factor));
156 SB_DATA (so, nvc0_blend_fac(cso->rt[i].alpha_dst_factor));
157 }
158 }
159 } else
160 if (blend_en) {
161 SB_BEGIN_3D(so, BLEND_EQUATION_RGB, 5);
162 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].rgb_func));
163 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_src_factor));
164 SB_DATA (so, nvc0_blend_fac(cso->rt[r].rgb_dst_factor));
165 SB_DATA (so, nvgl_blend_eqn(cso->rt[r].alpha_func));
166 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_src_factor));
167 SB_BEGIN_3D(so, BLEND_FUNC_DST_ALPHA, 1);
168 SB_DATA (so, nvc0_blend_fac(cso->rt[r].alpha_dst_factor));
169 }
170
171 SB_IMMED_3D(so, COLOR_MASK_COMMON, !indep_masks);
172 if (indep_masks) {
173 SB_BEGIN_3D(so, COLOR_MASK(0), 8);
174 for (i = 0; i < 8; ++i)
175 SB_DATA(so, nvc0_colormask(cso->rt[i].colormask));
176 } else {
177 SB_BEGIN_3D(so, COLOR_MASK(0), 1);
178 SB_DATA (so, nvc0_colormask(cso->rt[0].colormask));
179 }
180 }
181
182 ms = 0;
183 if (cso->alpha_to_coverage)
184 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE;
185 if (cso->alpha_to_one)
186 ms |= NVC0_3D_MULTISAMPLE_CTRL_ALPHA_TO_ONE;
187
188 SB_BEGIN_3D(so, MULTISAMPLE_CTRL, 1);
189 SB_DATA (so, ms);
190
191 assert(so->size <= ARRAY_SIZE(so->state));
192 return so;
193 }
194
195 static void
nvc0_blend_state_bind(struct pipe_context * pipe,void * hwcso)196 nvc0_blend_state_bind(struct pipe_context *pipe, void *hwcso)
197 {
198 struct nvc0_context *nvc0 = nvc0_context(pipe);
199
200 nvc0->blend = hwcso;
201 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND;
202 }
203
204 static void
nvc0_blend_state_delete(struct pipe_context * pipe,void * hwcso)205 nvc0_blend_state_delete(struct pipe_context *pipe, void *hwcso)
206 {
207 FREE(hwcso);
208 }
209
210 /* NOTE: ignoring line_last_pixel */
211 static void *
nvc0_rasterizer_state_create(struct pipe_context * pipe,const struct pipe_rasterizer_state * cso)212 nvc0_rasterizer_state_create(struct pipe_context *pipe,
213 const struct pipe_rasterizer_state *cso)
214 {
215 struct nvc0_rasterizer_stateobj *so;
216 uint16_t class_3d = nouveau_screen(pipe->screen)->class_3d;
217 uint32_t reg;
218
219 so = CALLOC_STRUCT(nvc0_rasterizer_stateobj);
220 if (!so)
221 return NULL;
222 so->pipe = *cso;
223
224 /* Scissor enables are handled in scissor state, we will not want to
225 * always emit 16 commands, one for each scissor rectangle, here.
226 */
227
228 SB_IMMED_3D(so, PROVOKING_VERTEX_LAST, !cso->flatshade_first);
229 SB_IMMED_3D(so, VERTEX_TWO_SIDE_ENABLE, cso->light_twoside);
230
231 SB_IMMED_3D(so, VERT_COLOR_CLAMP_EN, cso->clamp_vertex_color);
232 SB_BEGIN_3D(so, FRAG_COLOR_CLAMP_EN, 1);
233 SB_DATA (so, cso->clamp_fragment_color ? 0x11111111 : 0x00000000);
234
235 SB_IMMED_3D(so, MULTISAMPLE_ENABLE, cso->multisample);
236
237 SB_IMMED_3D(so, LINE_SMOOTH_ENABLE, cso->line_smooth);
238 if (cso->line_smooth || cso->multisample)
239 SB_BEGIN_3D(so, LINE_WIDTH_SMOOTH, 1);
240 else
241 SB_BEGIN_3D(so, LINE_WIDTH_ALIASED, 1);
242 SB_DATA (so, fui(cso->line_width));
243
244 SB_IMMED_3D(so, LINE_STIPPLE_ENABLE, cso->line_stipple_enable);
245 if (cso->line_stipple_enable) {
246 SB_BEGIN_3D(so, LINE_STIPPLE_PATTERN, 1);
247 SB_DATA (so, (cso->line_stipple_pattern << 8) |
248 cso->line_stipple_factor);
249
250 }
251
252 SB_IMMED_3D(so, VP_POINT_SIZE, cso->point_size_per_vertex);
253 if (!cso->point_size_per_vertex) {
254 SB_BEGIN_3D(so, POINT_SIZE, 1);
255 SB_DATA (so, fui(cso->point_size));
256 }
257
258 reg = (cso->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT) ?
259 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_UPPER_LEFT :
260 NVC0_3D_POINT_COORD_REPLACE_COORD_ORIGIN_LOWER_LEFT;
261
262 SB_BEGIN_3D(so, POINT_COORD_REPLACE, 1);
263 SB_DATA (so, ((cso->sprite_coord_enable & 0xff) << 3) | reg);
264 SB_IMMED_3D(so, POINT_SPRITE_ENABLE, cso->point_quad_rasterization);
265 SB_IMMED_3D(so, POINT_SMOOTH_ENABLE, cso->point_smooth);
266
267 if (class_3d >= GM200_3D_CLASS) {
268 SB_IMMED_3D(so, FILL_RECTANGLE,
269 cso->fill_front == PIPE_POLYGON_MODE_FILL_RECTANGLE ?
270 NVC0_3D_FILL_RECTANGLE_ENABLE : 0);
271 }
272
273 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_FRONT, 1);
274 SB_DATA (so, nvgl_polygon_mode(cso->fill_front));
275 SB_BEGIN_3D(so, MACRO_POLYGON_MODE_BACK, 1);
276 SB_DATA (so, nvgl_polygon_mode(cso->fill_back));
277 SB_IMMED_3D(so, POLYGON_SMOOTH_ENABLE, cso->poly_smooth);
278
279 SB_BEGIN_3D(so, CULL_FACE_ENABLE, 3);
280 SB_DATA (so, cso->cull_face != PIPE_FACE_NONE);
281 SB_DATA (so, cso->front_ccw ? NVC0_3D_FRONT_FACE_CCW :
282 NVC0_3D_FRONT_FACE_CW);
283 switch (cso->cull_face) {
284 case PIPE_FACE_FRONT_AND_BACK:
285 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT_AND_BACK);
286 break;
287 case PIPE_FACE_FRONT:
288 SB_DATA(so, NVC0_3D_CULL_FACE_FRONT);
289 break;
290 case PIPE_FACE_BACK:
291 default:
292 SB_DATA(so, NVC0_3D_CULL_FACE_BACK);
293 break;
294 }
295
296 SB_IMMED_3D(so, POLYGON_STIPPLE_ENABLE, cso->poly_stipple_enable);
297 SB_BEGIN_3D(so, POLYGON_OFFSET_POINT_ENABLE, 3);
298 SB_DATA (so, cso->offset_point);
299 SB_DATA (so, cso->offset_line);
300 SB_DATA (so, cso->offset_tri);
301
302 if (cso->offset_point || cso->offset_line || cso->offset_tri) {
303 SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1);
304 SB_DATA (so, fui(cso->offset_scale));
305 if (!cso->offset_units_unscaled) {
306 SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1);
307 SB_DATA (so, fui(cso->offset_units * 2.0f));
308 }
309 SB_BEGIN_3D(so, POLYGON_OFFSET_CLAMP, 1);
310 SB_DATA (so, fui(cso->offset_clamp));
311 }
312
313 if (cso->depth_clip_near)
314 reg = NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1;
315 else
316 reg =
317 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1 |
318 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_NEAR |
319 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_CLAMP_FAR |
320 NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK12_UNK2;
321
322 SB_BEGIN_3D(so, VIEW_VOLUME_CLIP_CTRL, 1);
323 SB_DATA (so, reg);
324
325 SB_IMMED_3D(so, DEPTH_CLIP_NEGATIVE_Z, cso->clip_halfz);
326
327 SB_IMMED_3D(so, PIXEL_CENTER_INTEGER, !cso->half_pixel_center);
328
329 if (class_3d >= GM200_3D_CLASS) {
330 if (cso->conservative_raster_mode != PIPE_CONSERVATIVE_RASTER_OFF) {
331 bool post_snap = cso->conservative_raster_mode ==
332 PIPE_CONSERVATIVE_RASTER_POST_SNAP;
333 uint32_t state = cso->subpixel_precision_x;
334 state |= cso->subpixel_precision_y << 4;
335 state |= (uint32_t)(cso->conservative_raster_dilate * 4) << 8;
336 state |= (post_snap || class_3d < GP100_3D_CLASS) ? 1 << 10 : 0;
337 SB_IMMED_3D(so, MACRO_CONSERVATIVE_RASTER_STATE, state);
338 } else {
339 SB_IMMED_3D(so, CONSERVATIVE_RASTER, 0);
340 }
341 }
342
343 assert(so->size <= ARRAY_SIZE(so->state));
344 return (void *)so;
345 }
346
347 static void
nvc0_rasterizer_state_bind(struct pipe_context * pipe,void * hwcso)348 nvc0_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
349 {
350 struct nvc0_context *nvc0 = nvc0_context(pipe);
351
352 nvc0->rast = hwcso;
353 nvc0->dirty_3d |= NVC0_NEW_3D_RASTERIZER;
354 }
355
356 static void
nvc0_rasterizer_state_delete(struct pipe_context * pipe,void * hwcso)357 nvc0_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso)
358 {
359 FREE(hwcso);
360 }
361
362 static void *
nvc0_zsa_state_create(struct pipe_context * pipe,const struct pipe_depth_stencil_alpha_state * cso)363 nvc0_zsa_state_create(struct pipe_context *pipe,
364 const struct pipe_depth_stencil_alpha_state *cso)
365 {
366 struct nvc0_zsa_stateobj *so = CALLOC_STRUCT(nvc0_zsa_stateobj);
367
368 so->pipe = *cso;
369
370 SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth_enabled);
371 if (cso->depth_enabled) {
372 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth_writemask);
373 SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
374 SB_DATA (so, nvgl_comparison_op(cso->depth_func));
375 }
376
377 SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth_bounds_test);
378 if (cso->depth_bounds_test) {
379 SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
380 SB_DATA (so, fui(cso->depth_bounds_min));
381 SB_DATA (so, fui(cso->depth_bounds_max));
382 }
383
384 if (cso->stencil[0].enabled) {
385 SB_BEGIN_3D(so, STENCIL_ENABLE, 5);
386 SB_DATA (so, 1);
387 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].fail_op));
388 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zfail_op));
389 SB_DATA (so, nvgl_stencil_op(cso->stencil[0].zpass_op));
390 SB_DATA (so, nvgl_comparison_op(cso->stencil[0].func));
391 SB_BEGIN_3D(so, STENCIL_FRONT_FUNC_MASK, 2);
392 SB_DATA (so, cso->stencil[0].valuemask);
393 SB_DATA (so, cso->stencil[0].writemask);
394 } else {
395 SB_IMMED_3D(so, STENCIL_ENABLE, 0);
396 }
397
398 if (cso->stencil[1].enabled) {
399 assert(cso->stencil[0].enabled);
400 SB_BEGIN_3D(so, STENCIL_TWO_SIDE_ENABLE, 5);
401 SB_DATA (so, 1);
402 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].fail_op));
403 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zfail_op));
404 SB_DATA (so, nvgl_stencil_op(cso->stencil[1].zpass_op));
405 SB_DATA (so, nvgl_comparison_op(cso->stencil[1].func));
406 SB_BEGIN_3D(so, STENCIL_BACK_MASK, 2);
407 SB_DATA (so, cso->stencil[1].writemask);
408 SB_DATA (so, cso->stencil[1].valuemask);
409 } else
410 if (cso->stencil[0].enabled) {
411 SB_IMMED_3D(so, STENCIL_TWO_SIDE_ENABLE, 0);
412 }
413
414 SB_IMMED_3D(so, ALPHA_TEST_ENABLE, cso->alpha_enabled);
415 if (cso->alpha_enabled) {
416 SB_BEGIN_3D(so, ALPHA_TEST_REF, 2);
417 SB_DATA (so, fui(cso->alpha_ref_value));
418 SB_DATA (so, nvgl_comparison_op(cso->alpha_func));
419 }
420
421 assert(so->size <= ARRAY_SIZE(so->state));
422 return (void *)so;
423 }
424
425 static void
nvc0_zsa_state_bind(struct pipe_context * pipe,void * hwcso)426 nvc0_zsa_state_bind(struct pipe_context *pipe, void *hwcso)
427 {
428 struct nvc0_context *nvc0 = nvc0_context(pipe);
429
430 nvc0->zsa = hwcso;
431 nvc0->dirty_3d |= NVC0_NEW_3D_ZSA;
432 }
433
434 static void
nvc0_zsa_state_delete(struct pipe_context * pipe,void * hwcso)435 nvc0_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
436 {
437 FREE(hwcso);
438 }
439
440 /* ====================== SAMPLERS AND TEXTURES ================================
441 */
442
443 #define NV50_TSC_WRAP_CASE(n) \
444 case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
445
446 static void
nvc0_sampler_state_delete(struct pipe_context * pipe,void * hwcso)447 nvc0_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
448 {
449 unsigned s, i;
450
451 for (s = 0; s < 6; ++s)
452 for (i = 0; i < nvc0_context(pipe)->num_samplers[s]; ++i)
453 if (nvc0_context(pipe)->samplers[s][i] == hwcso)
454 nvc0_context(pipe)->samplers[s][i] = NULL;
455
456 nvc0_screen_tsc_free(nvc0_context(pipe)->screen, nv50_tsc_entry(hwcso));
457
458 FREE(hwcso);
459 }
460
461 static inline void
nvc0_stage_sampler_states_bind(struct nvc0_context * nvc0,unsigned s,unsigned nr,void ** hwcsos)462 nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0,
463 unsigned s,
464 unsigned nr, void **hwcsos)
465 {
466 unsigned highest_found = 0;
467 unsigned i;
468
469 for (i = 0; i < nr; ++i) {
470 struct nv50_tsc_entry *hwcso = hwcsos ? nv50_tsc_entry(hwcsos[i]) : NULL;
471 struct nv50_tsc_entry *old = nvc0->samplers[s][i];
472
473 if (hwcso)
474 highest_found = i;
475
476 if (hwcso == old)
477 continue;
478 nvc0->samplers_dirty[s] |= 1 << i;
479
480 nvc0->samplers[s][i] = hwcso;
481 if (old)
482 nvc0_screen_tsc_unlock(nvc0->screen, old);
483 }
484 if (nr >= nvc0->num_samplers[s])
485 nvc0->num_samplers[s] = highest_found + 1;
486 }
487
488 static void
nvc0_bind_sampler_states(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned nr,void ** samplers)489 nvc0_bind_sampler_states(struct pipe_context *pipe,
490 enum pipe_shader_type shader,
491 unsigned start, unsigned nr, void **samplers)
492 {
493 const unsigned s = nvc0_shader_stage(shader);
494
495 assert(start == 0);
496 nvc0_stage_sampler_states_bind(nvc0_context(pipe), s, nr, samplers);
497
498 if (s == 5)
499 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SAMPLERS;
500 else
501 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SAMPLERS;
502 }
503
504
505 /* NOTE: only called when not referenced anywhere, won't be bound */
506 static void
nvc0_sampler_view_destroy(struct pipe_context * pipe,struct pipe_sampler_view * view)507 nvc0_sampler_view_destroy(struct pipe_context *pipe,
508 struct pipe_sampler_view *view)
509 {
510 pipe_resource_reference(&view->texture, NULL);
511
512 nvc0_screen_tic_free(nvc0_context(pipe)->screen, nv50_tic_entry(view));
513
514 FREE(nv50_tic_entry(view));
515 }
516
517 static inline void
nvc0_stage_set_sampler_views(struct nvc0_context * nvc0,int s,unsigned nr,bool take_ownership,struct pipe_sampler_view ** views)518 nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int s,
519 unsigned nr, bool take_ownership,
520 struct pipe_sampler_view **views)
521 {
522 unsigned i;
523
524 for (i = 0; i < nr; ++i) {
525 struct pipe_sampler_view *view = views ? views[i] : NULL;
526 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
527
528 if (view == nvc0->textures[s][i]) {
529 if (take_ownership)
530 pipe_sampler_view_reference(&view, NULL);
531 continue;
532 }
533 nvc0->textures_dirty[s] |= 1 << i;
534
535 if (view && view->texture) {
536 struct pipe_resource *res = view->texture;
537 if (res->target == PIPE_BUFFER &&
538 (res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
539 nvc0->textures_coherent[s] |= 1 << i;
540 else
541 nvc0->textures_coherent[s] &= ~(1 << i);
542 } else {
543 nvc0->textures_coherent[s] &= ~(1 << i);
544 }
545
546 if (old) {
547 if (s == 5)
548 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
549 else
550 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
551 nvc0_screen_tic_unlock(nvc0->screen, old);
552 }
553
554 if (take_ownership) {
555 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
556 nvc0->textures[s][i] = view;
557 } else {
558 pipe_sampler_view_reference(&nvc0->textures[s][i], view);
559 }
560 }
561
562 for (i = nr; i < nvc0->num_textures[s]; ++i) {
563 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
564 if (old) {
565 if (s == 5)
566 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEX(i));
567 else
568 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEX(s, i));
569 nvc0_screen_tic_unlock(nvc0->screen, old);
570 pipe_sampler_view_reference(&nvc0->textures[s][i], NULL);
571 }
572 }
573
574 nvc0->num_textures[s] = nr;
575 }
576
577 static void
nvc0_set_sampler_views(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned nr,unsigned unbind_num_trailing_slots,bool take_ownership,struct pipe_sampler_view ** views)578 nvc0_set_sampler_views(struct pipe_context *pipe, enum pipe_shader_type shader,
579 unsigned start, unsigned nr,
580 unsigned unbind_num_trailing_slots,
581 bool take_ownership,
582 struct pipe_sampler_view **views)
583 {
584 const unsigned s = nvc0_shader_stage(shader);
585
586 assert(start == 0);
587 nvc0_stage_set_sampler_views(nvc0_context(pipe), s, nr, take_ownership, views);
588
589 if (s == 5)
590 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_TEXTURES;
591 else
592 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_TEXTURES;
593 }
594
595 /* ============================= SHADERS =======================================
596 */
597
598 static void *
nvc0_sp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso,unsigned type)599 nvc0_sp_state_create(struct pipe_context *pipe,
600 const struct pipe_shader_state *cso, unsigned type)
601 {
602 struct nvc0_program *prog;
603
604 prog = CALLOC_STRUCT(nvc0_program);
605 if (!prog)
606 return NULL;
607
608 prog->type = type;
609
610 switch(cso->type) {
611 case PIPE_SHADER_IR_TGSI:
612 prog->nir = tgsi_to_nir(cso->tokens, pipe->screen, false);
613 break;
614 case PIPE_SHADER_IR_NIR:
615 prog->nir = cso->ir.nir;
616 break;
617 default:
618 assert(!"unsupported IR!");
619 free(prog);
620 return NULL;
621 }
622
623 if (cso->stream_output.num_outputs)
624 prog->stream_output = cso->stream_output;
625
626 prog->translated = nvc0_program_translate(
627 prog, nvc0_context(pipe)->screen->base.device->chipset,
628 nvc0_context(pipe)->screen->base.disk_shader_cache,
629 &nouveau_context(pipe)->debug);
630
631 return (void *)prog;
632 }
633
634 static void
nvc0_sp_state_delete(struct pipe_context * pipe,void * hwcso)635 nvc0_sp_state_delete(struct pipe_context *pipe, void *hwcso)
636 {
637 struct nvc0_context *nvc0 = nvc0_context(pipe);
638 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
639
640 simple_mtx_lock(&nvc0->screen->state_lock);
641 nvc0_program_destroy(nvc0_context(pipe), prog);
642 simple_mtx_unlock(&nvc0->screen->state_lock);
643
644 ralloc_free(prog->nir);
645 FREE(prog);
646 }
647
648 static void *
nvc0_vp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)649 nvc0_vp_state_create(struct pipe_context *pipe,
650 const struct pipe_shader_state *cso)
651 {
652 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_VERTEX);
653 }
654
655 static void
nvc0_vp_state_bind(struct pipe_context * pipe,void * hwcso)656 nvc0_vp_state_bind(struct pipe_context *pipe, void *hwcso)
657 {
658 struct nvc0_context *nvc0 = nvc0_context(pipe);
659
660 nvc0->vertprog = hwcso;
661 nvc0->dirty_3d |= NVC0_NEW_3D_VERTPROG;
662 }
663
664 static void *
nvc0_fp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)665 nvc0_fp_state_create(struct pipe_context *pipe,
666 const struct pipe_shader_state *cso)
667 {
668 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_FRAGMENT);
669 }
670
671 static void
nvc0_fp_state_bind(struct pipe_context * pipe,void * hwcso)672 nvc0_fp_state_bind(struct pipe_context *pipe, void *hwcso)
673 {
674 struct nvc0_context *nvc0 = nvc0_context(pipe);
675
676 nvc0->fragprog = hwcso;
677 nvc0->dirty_3d |= NVC0_NEW_3D_FRAGPROG;
678 }
679
680 static void *
nvc0_gp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)681 nvc0_gp_state_create(struct pipe_context *pipe,
682 const struct pipe_shader_state *cso)
683 {
684 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_GEOMETRY);
685 }
686
687 static void
nvc0_gp_state_bind(struct pipe_context * pipe,void * hwcso)688 nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
689 {
690 struct nvc0_context *nvc0 = nvc0_context(pipe);
691
692 nvc0->gmtyprog = hwcso;
693 nvc0->dirty_3d |= NVC0_NEW_3D_GMTYPROG;
694 }
695
696 static void *
nvc0_tcp_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)697 nvc0_tcp_state_create(struct pipe_context *pipe,
698 const struct pipe_shader_state *cso)
699 {
700 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
701 }
702
703 static void
nvc0_tcp_state_bind(struct pipe_context * pipe,void * hwcso)704 nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
705 {
706 struct nvc0_context *nvc0 = nvc0_context(pipe);
707
708 nvc0->tctlprog = hwcso;
709 nvc0->dirty_3d |= NVC0_NEW_3D_TCTLPROG;
710 }
711
712 static void *
nvc0_tep_state_create(struct pipe_context * pipe,const struct pipe_shader_state * cso)713 nvc0_tep_state_create(struct pipe_context *pipe,
714 const struct pipe_shader_state *cso)
715 {
716 return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
717 }
718
719 static void
nvc0_tep_state_bind(struct pipe_context * pipe,void * hwcso)720 nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
721 {
722 struct nvc0_context *nvc0 = nvc0_context(pipe);
723
724 nvc0->tevlprog = hwcso;
725 nvc0->dirty_3d |= NVC0_NEW_3D_TEVLPROG;
726 }
727
728 static void *
nvc0_cp_state_create(struct pipe_context * pipe,const struct pipe_compute_state * cso)729 nvc0_cp_state_create(struct pipe_context *pipe,
730 const struct pipe_compute_state *cso)
731 {
732 struct nvc0_program *prog;
733
734 prog = CALLOC_STRUCT(nvc0_program);
735 if (!prog)
736 return NULL;
737 prog->type = PIPE_SHADER_COMPUTE;
738
739 prog->cp.smem_size = cso->static_shared_mem;
740 prog->parm_size = cso->req_input_mem;
741
742 switch(cso->ir_type) {
743 case PIPE_SHADER_IR_TGSI: {
744 const struct tgsi_token *tokens = cso->prog;
745 prog->nir = tgsi_to_nir(tokens, pipe->screen, false);
746 break;
747 }
748 case PIPE_SHADER_IR_NIR:
749 prog->nir = (nir_shader *)cso->prog;
750 break;
751 case PIPE_SHADER_IR_NIR_SERIALIZED: {
752 struct blob_reader reader;
753 const struct pipe_binary_program_header *hdr = cso->prog;
754
755 blob_reader_init(&reader, hdr->blob, hdr->num_bytes);
756 prog->nir = nir_deserialize(NULL, pipe->screen->get_compiler_options(pipe->screen, PIPE_SHADER_IR_NIR, PIPE_SHADER_COMPUTE), &reader);
757 break;
758 }
759 default:
760 assert(!"unsupported IR!");
761 free(prog);
762 return NULL;
763 }
764
765 prog->translated = nvc0_program_translate(
766 prog, nvc0_context(pipe)->screen->base.device->chipset,
767 nvc0_context(pipe)->screen->base.disk_shader_cache,
768 &nouveau_context(pipe)->debug);
769
770 return (void *)prog;
771 }
772
773 static void
nvc0_cp_state_bind(struct pipe_context * pipe,void * hwcso)774 nvc0_cp_state_bind(struct pipe_context *pipe, void *hwcso)
775 {
776 struct nvc0_context *nvc0 = nvc0_context(pipe);
777
778 nvc0->compprog = hwcso;
779 nvc0->dirty_cp |= NVC0_NEW_CP_PROGRAM;
780 }
781
782 static void
nvc0_get_compute_state_info(struct pipe_context * pipe,void * hwcso,struct pipe_compute_state_object_info * info)783 nvc0_get_compute_state_info(struct pipe_context *pipe, void *hwcso,
784 struct pipe_compute_state_object_info *info)
785 {
786 struct nvc0_context *nvc0 = nvc0_context(pipe);
787 struct nvc0_program *prog = (struct nvc0_program *)hwcso;
788 uint16_t obj_class = nvc0->screen->compute->oclass;
789 uint32_t chipset = nvc0->screen->base.device->chipset;
790 uint32_t smregs;
791
792 // fermi and a handful of tegra devices have less gprs per SM
793 if (obj_class < NVE4_COMPUTE_CLASS || chipset == 0xea || chipset == 0x12b || chipset == 0x13b)
794 smregs = 32768;
795 else
796 smregs = 65536;
797
798 // TODO: not 100% sure about 8 for volta, but earlier reverse engineering indicates it
799 uint32_t gpr_alloc_size = obj_class >= GV100_COMPUTE_CLASS ? 8 : 4;
800 uint32_t threads = smregs / align(prog->num_gprs, gpr_alloc_size);
801
802 info->max_threads = MIN2(ROUND_DOWN_TO(threads, 32), 1024);
803 info->private_memory = prog->hdr[1] & 0xfffff0;
804 info->preferred_simd_size = 32;
805 info->simd_sizes = 32;
806 }
807
808 static void
nvc0_set_constant_buffer(struct pipe_context * pipe,enum pipe_shader_type shader,uint index,bool take_ownership,const struct pipe_constant_buffer * cb)809 nvc0_set_constant_buffer(struct pipe_context *pipe,
810 enum pipe_shader_type shader, uint index,
811 bool take_ownership,
812 const struct pipe_constant_buffer *cb)
813 {
814 struct nvc0_context *nvc0 = nvc0_context(pipe);
815 struct pipe_resource *res = cb ? cb->buffer : NULL;
816 const unsigned s = nvc0_shader_stage(shader);
817 const unsigned i = index;
818
819 if (unlikely(shader == PIPE_SHADER_COMPUTE)) {
820 if (nvc0->constbuf[s][i].user)
821 nvc0->constbuf[s][i].u.buf = NULL;
822 else
823 if (nvc0->constbuf[s][i].u.buf)
824 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_CB(i));
825
826 nvc0->dirty_cp |= NVC0_NEW_CP_CONSTBUF;
827 } else {
828 if (nvc0->constbuf[s][i].user)
829 nvc0->constbuf[s][i].u.buf = NULL;
830 else
831 if (nvc0->constbuf[s][i].u.buf)
832 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_CB(s, i));
833
834 nvc0->dirty_3d |= NVC0_NEW_3D_CONSTBUF;
835 }
836 nvc0->constbuf_dirty[s] |= 1 << i;
837
838 if (nvc0->constbuf[s][i].u.buf)
839 nv04_resource(nvc0->constbuf[s][i].u.buf)->cb_bindings[s] &= ~(1 << i);
840
841 if (take_ownership) {
842 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, NULL);
843 nvc0->constbuf[s][i].u.buf = res;
844 } else {
845 pipe_resource_reference(&nvc0->constbuf[s][i].u.buf, res);
846 }
847
848 nvc0->constbuf[s][i].user = (cb && cb->user_buffer) ? true : false;
849 if (nvc0->constbuf[s][i].user) {
850 nvc0->constbuf[s][i].u.data = cb->user_buffer;
851 nvc0->constbuf[s][i].size = MIN2(cb->buffer_size, 0x10000);
852 nvc0->constbuf_valid[s] |= 1 << i;
853 nvc0->constbuf_coherent[s] &= ~(1 << i);
854 } else
855 if (cb) {
856 nvc0->constbuf[s][i].offset = cb->buffer_offset;
857 nvc0->constbuf[s][i].size = MIN2(align(cb->buffer_size, 0x100), 0x10000);
858 nvc0->constbuf_valid[s] |= 1 << i;
859 if (res && res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
860 nvc0->constbuf_coherent[s] |= 1 << i;
861 else
862 nvc0->constbuf_coherent[s] &= ~(1 << i);
863 }
864 else {
865 nvc0->constbuf_valid[s] &= ~(1 << i);
866 nvc0->constbuf_coherent[s] &= ~(1 << i);
867 }
868 }
869
870 /* =============================================================================
871 */
872
873 static void
nvc0_set_blend_color(struct pipe_context * pipe,const struct pipe_blend_color * bcol)874 nvc0_set_blend_color(struct pipe_context *pipe,
875 const struct pipe_blend_color *bcol)
876 {
877 struct nvc0_context *nvc0 = nvc0_context(pipe);
878
879 nvc0->blend_colour = *bcol;
880 nvc0->dirty_3d |= NVC0_NEW_3D_BLEND_COLOUR;
881 }
882
883 static void
nvc0_set_stencil_ref(struct pipe_context * pipe,const struct pipe_stencil_ref sr)884 nvc0_set_stencil_ref(struct pipe_context *pipe,
885 const struct pipe_stencil_ref sr)
886 {
887 struct nvc0_context *nvc0 = nvc0_context(pipe);
888
889 nvc0->stencil_ref = sr;
890 nvc0->dirty_3d |= NVC0_NEW_3D_STENCIL_REF;
891 }
892
893 static void
nvc0_set_clip_state(struct pipe_context * pipe,const struct pipe_clip_state * clip)894 nvc0_set_clip_state(struct pipe_context *pipe,
895 const struct pipe_clip_state *clip)
896 {
897 struct nvc0_context *nvc0 = nvc0_context(pipe);
898
899 memcpy(nvc0->clip.ucp, clip->ucp, sizeof(clip->ucp));
900
901 nvc0->dirty_3d |= NVC0_NEW_3D_CLIP;
902 }
903
904 static void
nvc0_set_sample_mask(struct pipe_context * pipe,unsigned sample_mask)905 nvc0_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
906 {
907 struct nvc0_context *nvc0 = nvc0_context(pipe);
908
909 nvc0->sample_mask = sample_mask;
910 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_MASK;
911 }
912
913 static void
nvc0_set_min_samples(struct pipe_context * pipe,unsigned min_samples)914 nvc0_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
915 {
916 struct nvc0_context *nvc0 = nvc0_context(pipe);
917
918 if (nvc0->min_samples != min_samples) {
919 nvc0->min_samples = min_samples;
920 nvc0->dirty_3d |= NVC0_NEW_3D_MIN_SAMPLES;
921 }
922 }
923
924 static void
nvc0_set_framebuffer_state(struct pipe_context * pipe,const struct pipe_framebuffer_state * fb)925 nvc0_set_framebuffer_state(struct pipe_context *pipe,
926 const struct pipe_framebuffer_state *fb)
927 {
928 struct nvc0_context *nvc0 = nvc0_context(pipe);
929
930 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_FB);
931
932 util_copy_framebuffer_state(&nvc0->framebuffer, fb);
933
934 nvc0->dirty_3d |= NVC0_NEW_3D_FRAMEBUFFER | NVC0_NEW_3D_SAMPLE_LOCATIONS |
935 NVC0_NEW_3D_TEXTURES;
936 nvc0->dirty_cp |= NVC0_NEW_CP_TEXTURES;
937 }
938
939 static void
nvc0_set_sample_locations(struct pipe_context * pipe,size_t size,const uint8_t * locations)940 nvc0_set_sample_locations(struct pipe_context *pipe,
941 size_t size, const uint8_t *locations)
942 {
943 struct nvc0_context *nvc0 = nvc0_context(pipe);
944
945 nvc0->sample_locations_enabled = size && locations;
946 if (size > sizeof(nvc0->sample_locations))
947 size = sizeof(nvc0->sample_locations);
948 memcpy(nvc0->sample_locations, locations, size);
949
950 nvc0->dirty_3d |= NVC0_NEW_3D_SAMPLE_LOCATIONS;
951 }
952
953 static void
nvc0_set_polygon_stipple(struct pipe_context * pipe,const struct pipe_poly_stipple * stipple)954 nvc0_set_polygon_stipple(struct pipe_context *pipe,
955 const struct pipe_poly_stipple *stipple)
956 {
957 struct nvc0_context *nvc0 = nvc0_context(pipe);
958
959 nvc0->stipple = *stipple;
960 nvc0->dirty_3d |= NVC0_NEW_3D_STIPPLE;
961 }
962
963 static void
nvc0_set_scissor_states(struct pipe_context * pipe,unsigned start_slot,unsigned num_scissors,const struct pipe_scissor_state * scissor)964 nvc0_set_scissor_states(struct pipe_context *pipe,
965 unsigned start_slot,
966 unsigned num_scissors,
967 const struct pipe_scissor_state *scissor)
968 {
969 struct nvc0_context *nvc0 = nvc0_context(pipe);
970 int i;
971
972 assert(start_slot + num_scissors <= NVC0_MAX_VIEWPORTS);
973 for (i = 0; i < num_scissors; i++) {
974 if (!memcmp(&nvc0->scissors[start_slot + i], &scissor[i], sizeof(*scissor)))
975 continue;
976 nvc0->scissors[start_slot + i] = scissor[i];
977 nvc0->scissors_dirty |= 1 << (start_slot + i);
978 nvc0->dirty_3d |= NVC0_NEW_3D_SCISSOR;
979 }
980 }
981
982 static void
nvc0_set_viewport_states(struct pipe_context * pipe,unsigned start_slot,unsigned num_viewports,const struct pipe_viewport_state * vpt)983 nvc0_set_viewport_states(struct pipe_context *pipe,
984 unsigned start_slot,
985 unsigned num_viewports,
986 const struct pipe_viewport_state *vpt)
987 {
988 struct nvc0_context *nvc0 = nvc0_context(pipe);
989 int i;
990
991 assert(start_slot + num_viewports <= NVC0_MAX_VIEWPORTS);
992 for (i = 0; i < num_viewports; i++) {
993 if (!memcmp(&nvc0->viewports[start_slot + i], &vpt[i], sizeof(*vpt)))
994 continue;
995 nvc0->viewports[start_slot + i] = vpt[i];
996 nvc0->viewports_dirty |= 1 << (start_slot + i);
997 nvc0->dirty_3d |= NVC0_NEW_3D_VIEWPORT;
998 }
999
1000 }
1001
1002 static void
nvc0_set_window_rectangles(struct pipe_context * pipe,bool include,unsigned num_rectangles,const struct pipe_scissor_state * rectangles)1003 nvc0_set_window_rectangles(struct pipe_context *pipe,
1004 bool include,
1005 unsigned num_rectangles,
1006 const struct pipe_scissor_state *rectangles)
1007 {
1008 struct nvc0_context *nvc0 = nvc0_context(pipe);
1009
1010 nvc0->window_rect.inclusive = include;
1011 nvc0->window_rect.rects = MIN2(num_rectangles, NVC0_MAX_WINDOW_RECTANGLES);
1012 memcpy(nvc0->window_rect.rect, rectangles,
1013 sizeof(struct pipe_scissor_state) * nvc0->window_rect.rects);
1014
1015 nvc0->dirty_3d |= NVC0_NEW_3D_WINDOW_RECTS;
1016 }
1017
1018 static void
nvc0_set_tess_state(struct pipe_context * pipe,const float default_tess_outer[4],const float default_tess_inner[2])1019 nvc0_set_tess_state(struct pipe_context *pipe,
1020 const float default_tess_outer[4],
1021 const float default_tess_inner[2])
1022 {
1023 struct nvc0_context *nvc0 = nvc0_context(pipe);
1024
1025 memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
1026 memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
1027 nvc0->dirty_3d |= NVC0_NEW_3D_TESSFACTOR;
1028 }
1029
1030 static void
nvc0_set_patch_vertices(struct pipe_context * pipe,uint8_t patch_vertices)1031 nvc0_set_patch_vertices(struct pipe_context *pipe, uint8_t patch_vertices)
1032 {
1033 struct nvc0_context *nvc0 = nvc0_context(pipe);
1034
1035 nvc0->patch_vertices = patch_vertices;
1036 }
1037
1038 static void
nvc0_set_vertex_buffers(struct pipe_context * pipe,unsigned count,const struct pipe_vertex_buffer * vb)1039 nvc0_set_vertex_buffers(struct pipe_context *pipe,
1040 unsigned count,
1041 const struct pipe_vertex_buffer *vb)
1042 {
1043 struct nvc0_context *nvc0 = nvc0_context(pipe);
1044 unsigned i;
1045
1046 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX);
1047 nvc0->dirty_3d |= NVC0_NEW_3D_ARRAYS;
1048
1049 unsigned last_count = nvc0->num_vtxbufs;
1050 util_set_vertex_buffers_count(nvc0->vtxbuf, &nvc0->num_vtxbufs, vb,
1051 count, true);
1052
1053 unsigned clear_mask =
1054 last_count > count ? BITFIELD_RANGE(count, last_count - count) : 0;
1055 nvc0->vbo_user &= clear_mask;
1056 nvc0->constant_vbos &= clear_mask;
1057 nvc0->vtxbufs_coherent &= clear_mask;
1058
1059 if (!vb) {
1060 clear_mask = ~u_bit_consecutive(0, count);
1061 nvc0->vbo_user &= clear_mask;
1062 nvc0->constant_vbos &= clear_mask;
1063 nvc0->vtxbufs_coherent &= clear_mask;
1064 return;
1065 }
1066
1067 for (i = 0; i < count; ++i) {
1068 unsigned dst_index = i;
1069
1070 if (vb[i].is_user_buffer) {
1071 nvc0->vbo_user |= 1 << dst_index;
1072 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1073 } else {
1074 nvc0->vbo_user &= ~(1 << dst_index);
1075
1076 if (vb[i].buffer.resource &&
1077 vb[i].buffer.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT)
1078 nvc0->vtxbufs_coherent |= (1 << dst_index);
1079 else
1080 nvc0->vtxbufs_coherent &= ~(1 << dst_index);
1081 }
1082 }
1083 }
1084
1085 static void
nvc0_vertex_state_bind(struct pipe_context * pipe,void * hwcso)1086 nvc0_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
1087 {
1088 struct nvc0_context *nvc0 = nvc0_context(pipe);
1089
1090 nvc0->vertex = hwcso;
1091 nvc0->dirty_3d |= NVC0_NEW_3D_VERTEX;
1092 }
1093
1094 static struct pipe_stream_output_target *
nvc0_so_target_create(struct pipe_context * pipe,struct pipe_resource * res,unsigned offset,unsigned size)1095 nvc0_so_target_create(struct pipe_context *pipe,
1096 struct pipe_resource *res,
1097 unsigned offset, unsigned size)
1098 {
1099 struct nv04_resource *buf = (struct nv04_resource *)res;
1100 struct nvc0_so_target *targ = MALLOC_STRUCT(nvc0_so_target);
1101 if (!targ)
1102 return NULL;
1103
1104 targ->pq = pipe->create_query(pipe, NVC0_HW_QUERY_TFB_BUFFER_OFFSET, 0);
1105 if (!targ->pq) {
1106 FREE(targ);
1107 return NULL;
1108 }
1109 targ->clean = true;
1110
1111 targ->pipe.buffer_size = size;
1112 targ->pipe.buffer_offset = offset;
1113 targ->pipe.context = pipe;
1114 targ->pipe.buffer = NULL;
1115 pipe_resource_reference(&targ->pipe.buffer, res);
1116 pipe_reference_init(&targ->pipe.reference, 1);
1117
1118 assert(buf->base.target == PIPE_BUFFER);
1119 util_range_add(&buf->base, &buf->valid_buffer_range, offset, offset + size);
1120
1121 return &targ->pipe;
1122 }
1123
1124 static void
nvc0_so_target_save_offset(struct pipe_context * pipe,struct pipe_stream_output_target * ptarg,unsigned index,bool * serialize)1125 nvc0_so_target_save_offset(struct pipe_context *pipe,
1126 struct pipe_stream_output_target *ptarg,
1127 unsigned index, bool *serialize)
1128 {
1129 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1130
1131 if (*serialize) {
1132 *serialize = false;
1133 PUSH_SPACE(nvc0_context(pipe)->base.pushbuf, 1);
1134 IMMED_NVC0(nvc0_context(pipe)->base.pushbuf, NVC0_3D(SERIALIZE), 0);
1135
1136 NOUVEAU_DRV_STAT(nouveau_screen(pipe->screen), gpu_serialize_count, 1);
1137 }
1138
1139 nvc0_query(targ->pq)->index = index;
1140 pipe->end_query(pipe, targ->pq);
1141 }
1142
1143 static void
nvc0_so_target_destroy(struct pipe_context * pipe,struct pipe_stream_output_target * ptarg)1144 nvc0_so_target_destroy(struct pipe_context *pipe,
1145 struct pipe_stream_output_target *ptarg)
1146 {
1147 struct nvc0_so_target *targ = nvc0_so_target(ptarg);
1148 pipe->destroy_query(pipe, targ->pq);
1149 pipe_resource_reference(&targ->pipe.buffer, NULL);
1150 FREE(targ);
1151 }
1152
1153 static void
nvc0_set_transform_feedback_targets(struct pipe_context * pipe,unsigned num_targets,struct pipe_stream_output_target ** targets,const unsigned * offsets)1154 nvc0_set_transform_feedback_targets(struct pipe_context *pipe,
1155 unsigned num_targets,
1156 struct pipe_stream_output_target **targets,
1157 const unsigned *offsets)
1158 {
1159 struct nvc0_context *nvc0 = nvc0_context(pipe);
1160 unsigned i;
1161 bool serialize = true;
1162
1163 assert(num_targets <= 4);
1164
1165 for (i = 0; i < num_targets; ++i) {
1166 const bool changed = nvc0->tfbbuf[i] != targets[i];
1167 const bool append = (offsets[i] == ((unsigned)-1));
1168 if (!changed && append)
1169 continue;
1170 nvc0->tfbbuf_dirty |= 1 << i;
1171
1172 if (nvc0->tfbbuf[i] && changed)
1173 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1174
1175 if (targets[i] && !append)
1176 nvc0_so_target(targets[i])->clean = true;
1177
1178 pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
1179 }
1180 for (; i < nvc0->num_tfbbufs; ++i) {
1181 if (nvc0->tfbbuf[i]) {
1182 nvc0->tfbbuf_dirty |= 1 << i;
1183 nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
1184 pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
1185 }
1186 }
1187 nvc0->num_tfbbufs = num_targets;
1188
1189 if (nvc0->tfbbuf_dirty) {
1190 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TFB);
1191 nvc0->dirty_3d |= NVC0_NEW_3D_TFB_TARGETS;
1192 }
1193 }
1194
1195 static void
nvc0_bind_surfaces_range(struct nvc0_context * nvc0,const unsigned t,unsigned start,unsigned nr,struct pipe_surface ** psurfaces)1196 nvc0_bind_surfaces_range(struct nvc0_context *nvc0, const unsigned t,
1197 unsigned start, unsigned nr,
1198 struct pipe_surface **psurfaces)
1199 {
1200 const unsigned end = start + nr;
1201 const unsigned mask = ((1 << nr) - 1) << start;
1202 unsigned i;
1203
1204 if (psurfaces) {
1205 for (i = start; i < end; ++i) {
1206 const unsigned p = i - start;
1207 if (psurfaces[p])
1208 nvc0->surfaces_valid[t] |= (1 << i);
1209 else
1210 nvc0->surfaces_valid[t] &= ~(1 << i);
1211 pipe_surface_reference(&nvc0->surfaces[t][i], psurfaces[p]);
1212 }
1213 } else {
1214 for (i = start; i < end; ++i)
1215 pipe_surface_reference(&nvc0->surfaces[t][i], NULL);
1216 nvc0->surfaces_valid[t] &= ~mask;
1217 }
1218 nvc0->surfaces_dirty[t] |= mask;
1219
1220 if (t == 0)
1221 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1222 else
1223 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1224 }
1225
1226 static void
nvc0_set_compute_resources(struct pipe_context * pipe,unsigned start,unsigned nr,struct pipe_surface ** resources)1227 nvc0_set_compute_resources(struct pipe_context *pipe,
1228 unsigned start, unsigned nr,
1229 struct pipe_surface **resources)
1230 {
1231 nvc0_bind_surfaces_range(nvc0_context(pipe), 1, start, nr, resources);
1232
1233 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1234 }
1235
1236 static bool
nvc0_bind_images_range(struct nvc0_context * nvc0,const unsigned s,unsigned start,unsigned nr,const struct pipe_image_view * pimages)1237 nvc0_bind_images_range(struct nvc0_context *nvc0, const unsigned s,
1238 unsigned start, unsigned nr,
1239 const struct pipe_image_view *pimages)
1240 {
1241 const unsigned end = start + nr;
1242 unsigned mask = 0;
1243 unsigned i;
1244
1245 assert(s < 6);
1246
1247 if (pimages) {
1248 for (i = start; i < end; ++i) {
1249 struct pipe_image_view *img = &nvc0->images[s][i];
1250 const unsigned p = i - start;
1251
1252 if (img->resource == pimages[p].resource &&
1253 img->format == pimages[p].format &&
1254 img->access == pimages[p].access) {
1255 if (img->resource == NULL)
1256 continue;
1257 if (img->resource->target == PIPE_BUFFER &&
1258 img->u.buf.offset == pimages[p].u.buf.offset &&
1259 img->u.buf.size == pimages[p].u.buf.size)
1260 continue;
1261 if (img->resource->target != PIPE_BUFFER &&
1262 img->u.tex.first_layer == pimages[p].u.tex.first_layer &&
1263 img->u.tex.last_layer == pimages[p].u.tex.last_layer &&
1264 img->u.tex.level == pimages[p].u.tex.level)
1265 continue;
1266 }
1267
1268 mask |= (1 << i);
1269 if (pimages[p].resource)
1270 nvc0->images_valid[s] |= (1 << i);
1271 else
1272 nvc0->images_valid[s] &= ~(1 << i);
1273
1274 img->format = pimages[p].format;
1275 img->access = pimages[p].access;
1276 if (pimages[p].resource && pimages[p].resource->target == PIPE_BUFFER)
1277 img->u.buf = pimages[p].u.buf;
1278 else
1279 img->u.tex = pimages[p].u.tex;
1280
1281 pipe_resource_reference(
1282 &img->resource, pimages[p].resource);
1283
1284 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1285 if (nvc0->images_tic[s][i]) {
1286 struct nv50_tic_entry *old =
1287 nv50_tic_entry(nvc0->images_tic[s][i]);
1288 nvc0_screen_tic_unlock(nvc0->screen, old);
1289 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1290 }
1291
1292 nvc0->images_tic[s][i] =
1293 gm107_create_texture_view_from_image(&nvc0->base.pipe,
1294 &pimages[p]);
1295 }
1296 }
1297 if (!mask)
1298 return false;
1299 } else {
1300 mask = ((1 << nr) - 1) << start;
1301 if (!(nvc0->images_valid[s] & mask))
1302 return false;
1303 for (i = start; i < end; ++i) {
1304 pipe_resource_reference(&nvc0->images[s][i].resource, NULL);
1305 if (nvc0->screen->base.class_3d >= GM107_3D_CLASS) {
1306 struct nv50_tic_entry *old = nv50_tic_entry(nvc0->images_tic[s][i]);
1307 if (old) {
1308 nvc0_screen_tic_unlock(nvc0->screen, old);
1309 pipe_sampler_view_reference(&nvc0->images_tic[s][i], NULL);
1310 }
1311 }
1312 }
1313 nvc0->images_valid[s] &= ~mask;
1314 }
1315 nvc0->images_dirty[s] |= mask;
1316
1317 if (s == 5)
1318 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
1319 else
1320 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
1321
1322 return true;
1323 }
1324
1325 static void
nvc0_set_shader_images(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned nr,unsigned unbind_num_trailing_slots,const struct pipe_image_view * images)1326 nvc0_set_shader_images(struct pipe_context *pipe,
1327 enum pipe_shader_type shader,
1328 unsigned start, unsigned nr,
1329 unsigned unbind_num_trailing_slots,
1330 const struct pipe_image_view *images)
1331 {
1332 const unsigned s = nvc0_shader_stage(shader);
1333
1334 nvc0_bind_images_range(nvc0_context(pipe), s, start + nr,
1335 unbind_num_trailing_slots, NULL);
1336
1337 if (!nvc0_bind_images_range(nvc0_context(pipe), s, start, nr, images))
1338 return;
1339
1340 if (s == 5)
1341 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_SURFACES;
1342 else
1343 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_SURFACES;
1344 }
1345
1346 static bool
nvc0_bind_buffers_range(struct nvc0_context * nvc0,const unsigned t,unsigned start,unsigned nr,const struct pipe_shader_buffer * pbuffers)1347 nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t,
1348 unsigned start, unsigned nr,
1349 const struct pipe_shader_buffer *pbuffers)
1350 {
1351 const unsigned end = start + nr;
1352 unsigned mask = 0;
1353 unsigned i;
1354
1355 assert(t < 6);
1356
1357 if (pbuffers) {
1358 for (i = start; i < end; ++i) {
1359 struct pipe_shader_buffer *buf = &nvc0->buffers[t][i];
1360 const unsigned p = i - start;
1361 if (buf->buffer == pbuffers[p].buffer &&
1362 buf->buffer_offset == pbuffers[p].buffer_offset &&
1363 buf->buffer_size == pbuffers[p].buffer_size)
1364 continue;
1365
1366 mask |= (1 << i);
1367 if (pbuffers[p].buffer)
1368 nvc0->buffers_valid[t] |= (1 << i);
1369 else
1370 nvc0->buffers_valid[t] &= ~(1 << i);
1371 buf->buffer_offset = pbuffers[p].buffer_offset;
1372 buf->buffer_size = pbuffers[p].buffer_size;
1373 pipe_resource_reference(&buf->buffer, pbuffers[p].buffer);
1374 }
1375 if (!mask)
1376 return false;
1377 } else {
1378 mask = ((1 << nr) - 1) << start;
1379 if (!(nvc0->buffers_valid[t] & mask))
1380 return false;
1381 for (i = start; i < end; ++i)
1382 pipe_resource_reference(&nvc0->buffers[t][i].buffer, NULL);
1383 nvc0->buffers_valid[t] &= ~mask;
1384 }
1385 nvc0->buffers_dirty[t] |= mask;
1386
1387 if (t == 5)
1388 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF);
1389 else
1390 nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BUF);
1391
1392 return true;
1393 }
1394
1395 static void
nvc0_set_shader_buffers(struct pipe_context * pipe,enum pipe_shader_type shader,unsigned start,unsigned nr,const struct pipe_shader_buffer * buffers,unsigned writable_bitmask)1396 nvc0_set_shader_buffers(struct pipe_context *pipe,
1397 enum pipe_shader_type shader,
1398 unsigned start, unsigned nr,
1399 const struct pipe_shader_buffer *buffers,
1400 unsigned writable_bitmask)
1401 {
1402 const unsigned s = nvc0_shader_stage(shader);
1403 if (!nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers))
1404 return;
1405
1406 if (s == 5)
1407 nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_BUFFERS;
1408 else
1409 nvc0_context(pipe)->dirty_3d |= NVC0_NEW_3D_BUFFERS;
1410 }
1411
1412 static inline void
nvc0_set_global_handle(uint32_t * phandle,struct pipe_resource * res)1413 nvc0_set_global_handle(uint32_t *phandle, struct pipe_resource *res)
1414 {
1415 struct nv04_resource *buf = nv04_resource(res);
1416 if (buf) {
1417 uint64_t address = buf->address + *phandle;
1418 /* even though it's a pointer to uint32_t that's fine */
1419 memcpy(phandle, &address, 8);
1420 } else {
1421 *phandle = 0;
1422 }
1423 }
1424
1425 static void
nvc0_set_global_bindings(struct pipe_context * pipe,unsigned start,unsigned nr,struct pipe_resource ** resources,uint32_t ** handles)1426 nvc0_set_global_bindings(struct pipe_context *pipe,
1427 unsigned start, unsigned nr,
1428 struct pipe_resource **resources,
1429 uint32_t **handles)
1430 {
1431 struct nvc0_context *nvc0 = nvc0_context(pipe);
1432 struct pipe_resource **ptr;
1433 unsigned i;
1434 const unsigned end = start + nr;
1435
1436 if (!nr)
1437 return;
1438
1439 if (nvc0->global_residents.size < (end * sizeof(struct pipe_resource *))) {
1440 const unsigned old_size = nvc0->global_residents.size;
1441 if (util_dynarray_resize(&nvc0->global_residents, struct pipe_resource *, end)) {
1442 memset((uint8_t *)nvc0->global_residents.data + old_size, 0,
1443 nvc0->global_residents.size - old_size);
1444 } else {
1445 NOUVEAU_ERR("Could not resize global residents array\n");
1446 return;
1447 }
1448 }
1449
1450 if (resources) {
1451 ptr = util_dynarray_element(
1452 &nvc0->global_residents, struct pipe_resource *, start);
1453 for (i = 0; i < nr; ++i) {
1454 pipe_resource_reference(&ptr[i], resources[i]);
1455 nvc0_set_global_handle(handles[i], resources[i]);
1456 }
1457 } else {
1458 ptr = util_dynarray_element(
1459 &nvc0->global_residents, struct pipe_resource *, start);
1460 for (i = 0; i < nr; ++i)
1461 pipe_resource_reference(&ptr[i], NULL);
1462 }
1463
1464 nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
1465
1466 nvc0->dirty_cp |= NVC0_NEW_CP_GLOBALS;
1467 }
1468
1469 void
nvc0_init_state_functions(struct nvc0_context * nvc0)1470 nvc0_init_state_functions(struct nvc0_context *nvc0)
1471 {
1472 struct pipe_context *pipe = &nvc0->base.pipe;
1473
1474 pipe->create_blend_state = nvc0_blend_state_create;
1475 pipe->bind_blend_state = nvc0_blend_state_bind;
1476 pipe->delete_blend_state = nvc0_blend_state_delete;
1477
1478 pipe->create_rasterizer_state = nvc0_rasterizer_state_create;
1479 pipe->bind_rasterizer_state = nvc0_rasterizer_state_bind;
1480 pipe->delete_rasterizer_state = nvc0_rasterizer_state_delete;
1481
1482 pipe->create_depth_stencil_alpha_state = nvc0_zsa_state_create;
1483 pipe->bind_depth_stencil_alpha_state = nvc0_zsa_state_bind;
1484 pipe->delete_depth_stencil_alpha_state = nvc0_zsa_state_delete;
1485
1486 pipe->create_sampler_state = nv50_sampler_state_create;
1487 pipe->delete_sampler_state = nvc0_sampler_state_delete;
1488 pipe->bind_sampler_states = nvc0_bind_sampler_states;
1489
1490 pipe->create_sampler_view = nvc0_create_sampler_view;
1491 pipe->sampler_view_destroy = nvc0_sampler_view_destroy;
1492 pipe->set_sampler_views = nvc0_set_sampler_views;
1493
1494 pipe->create_vs_state = nvc0_vp_state_create;
1495 pipe->create_fs_state = nvc0_fp_state_create;
1496 pipe->create_gs_state = nvc0_gp_state_create;
1497 pipe->create_tcs_state = nvc0_tcp_state_create;
1498 pipe->create_tes_state = nvc0_tep_state_create;
1499 pipe->bind_vs_state = nvc0_vp_state_bind;
1500 pipe->bind_fs_state = nvc0_fp_state_bind;
1501 pipe->bind_gs_state = nvc0_gp_state_bind;
1502 pipe->bind_tcs_state = nvc0_tcp_state_bind;
1503 pipe->bind_tes_state = nvc0_tep_state_bind;
1504 pipe->delete_vs_state = nvc0_sp_state_delete;
1505 pipe->delete_fs_state = nvc0_sp_state_delete;
1506 pipe->delete_gs_state = nvc0_sp_state_delete;
1507 pipe->delete_tcs_state = nvc0_sp_state_delete;
1508 pipe->delete_tes_state = nvc0_sp_state_delete;
1509
1510 pipe->create_compute_state = nvc0_cp_state_create;
1511 pipe->bind_compute_state = nvc0_cp_state_bind;
1512 pipe->get_compute_state_info = nvc0_get_compute_state_info;
1513 pipe->delete_compute_state = nvc0_sp_state_delete;
1514
1515 pipe->set_blend_color = nvc0_set_blend_color;
1516 pipe->set_stencil_ref = nvc0_set_stencil_ref;
1517 pipe->set_clip_state = nvc0_set_clip_state;
1518 pipe->set_sample_mask = nvc0_set_sample_mask;
1519 pipe->set_min_samples = nvc0_set_min_samples;
1520 pipe->set_constant_buffer = nvc0_set_constant_buffer;
1521 pipe->set_framebuffer_state = nvc0_set_framebuffer_state;
1522 pipe->set_sample_locations = nvc0_set_sample_locations;
1523 pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
1524 pipe->set_scissor_states = nvc0_set_scissor_states;
1525 pipe->set_viewport_states = nvc0_set_viewport_states;
1526 pipe->set_window_rectangles = nvc0_set_window_rectangles;
1527 pipe->set_tess_state = nvc0_set_tess_state;
1528 pipe->set_patch_vertices = nvc0_set_patch_vertices;
1529
1530 pipe->create_vertex_elements_state = nvc0_vertex_state_create;
1531 pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
1532 pipe->bind_vertex_elements_state = nvc0_vertex_state_bind;
1533
1534 pipe->set_vertex_buffers = nvc0_set_vertex_buffers;
1535
1536 pipe->create_stream_output_target = nvc0_so_target_create;
1537 pipe->stream_output_target_destroy = nvc0_so_target_destroy;
1538 pipe->set_stream_output_targets = nvc0_set_transform_feedback_targets;
1539
1540 pipe->set_global_binding = nvc0_set_global_bindings;
1541 pipe->set_compute_resources = nvc0_set_compute_resources;
1542 pipe->set_shader_images = nvc0_set_shader_images;
1543 pipe->set_shader_buffers = nvc0_set_shader_buffers;
1544
1545 nvc0->sample_mask = ~0;
1546 nvc0->min_samples = 1;
1547 nvc0->default_tess_outer[0] =
1548 nvc0->default_tess_outer[1] =
1549 nvc0->default_tess_outer[2] =
1550 nvc0->default_tess_outer[3] = 1.0;
1551 nvc0->default_tess_inner[0] =
1552 nvc0->default_tess_inner[1] = 1.0;
1553 }
1554