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12

/linux-6.14.4/arch/riscv/boot/dts/microchip/
Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
11 compatible = "microchip,mpfs";
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
[all …]
Dmpfs-icicle-kit-fabric.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
5 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
6 "microchip,mpfs";
9 compatible = "microchip,corepwm-rtl-v4";
11 microchip,sync-update-mask = /bits/ 32 <0>;
12 #pwm-cells = <3>;
18 compatible = "microchip,corei2c-rtl-v7";
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]
Dmpfs-icicle-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
6 #include "mpfs.dtsi"
7 #include "mpfs-icicle-kit-fabric.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
12 model = "Microchip PolarFire-SoC Icicle Kit";
13 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
14 "microchip,mpfs";
[all …]
Dmpfs-beaglev-fire.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include "mpfs.dtsi"
8 #include "mpfs-beaglev-fire-fabric.dtsi"
10 /* Clock frequency (in Hz) of MTIMER */
14 #address-cells = <2>;
15 #size-cells = <2>;
16 model = "BeagleBoard BeagleV-Fire";
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Dmpfs-polarberry.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2022 Microchip Technology Inc */
4 /dts-v1/;
6 #include "mpfs.dtsi"
7 #include "mpfs-polarberry-fabric.dtsi"
11 compatible = "sundance,polarberry", "microchip,mpfs";
19 stdout-path = "serial0:115200n8";
38 phy-mode = "sgmii";
39 phy-handle = <&phy0>;
44 phy-mode = "sgmii";
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Dmpfs-sev-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include "mpfs.dtsi"
7 #include "mpfs-sev-kit-fabric.dtsi"
10 #address-cells = <2>;
11 #size-cells = <2>;
12 model = "Microchip PolarFire-SoC SEV Kit";
13 compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";
25 stdout-path = "serial1:115200n8";
28 reserved-memory {
[all …]
Dmpfs-tysom-m.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Original all-in-one devicetree:
4 * Copyright (C) 2020-2022 - Aldec
6 * Copyright (C) 2022 - Conor Dooley <[email protected]>
9 /dts-v1/;
11 #include "mpfs.dtsi"
12 #include "mpfs-tysom-m-fabric.dtsi"
15 model = "Aldec TySOM-M-MPFS250T-REV2";
16 compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs";
31 stdout-path = "serial1:115200n8";
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Dmpfs-m100pfsevp.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Original all-in-one devicetree:
4 * Copyright (C) 2021-2022 - Wolfgang Grandegger <wg@aries-embedded.de>
6 * Copyright (C) 2022 - Conor Dooley <[email protected]>
8 /dts-v1/;
10 #include "mpfs.dtsi"
11 #include "mpfs-m100pfs-fabric.dtsi"
15 compatible = "aries,m100pfsevp", "microchip,mpfs";
30 stdout-path = "serial1:115200n8";
63 pmic-irq-hog {
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/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dmicrochip,mpfs-clkcfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire Clock Control Module
10 - Daire McNamara <[email protected]>
13 Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
17 user nodes by the CLKCFG node phandle and the clock index in the group, from
22 const: microchip,mpfs-clkcfg
26 - description: |
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Dmicrochip,mpfs-ccc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry
10 - Conor Dooley <[email protected]>
13 Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of
16 https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
20 const: microchip,mpfs-ccc
24 - description: PLL0's control registers
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/linux-6.14.4/Documentation/devicetree/bindings/rtc/
Dmicrochip,mpfs-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/microchip,mpfs-rtc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Microchip PolarFire Soc (MPFS) RTC
11 - $ref: rtc.yaml#
14 - Daire McNamara <[email protected]>
19 - items:
20 - const: microchip,pic64gx-rtc
21 - const: microchip,mpfs-rtc
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/linux-6.14.4/Documentation/devicetree/bindings/spi/
Dmicrochip,mpfs-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Conor Dooley <[email protected]>
19 - items:
20 - enum:
21 - microchip,mpfs-qspi
22 - microchip,pic64gx-qspi
23 - const: microchip,coreqspi-rtl-v2
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/linux-6.14.4/Documentation/devicetree/bindings/usb/
Dmicrochip,mpfs-musb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/microchip,mpfs-musb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip MPFS USB Controller
10 - $ref: usb-drd.yaml#
13 - Conor Dooley <[email protected]>
18 - items:
19 - const: microchip,pic64gx-musb
20 - const: microchip,mpfs-musb
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/can/
Dmicrochip,mpfs-can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/microchip,mpfs-can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Microchip PolarFire SoC (MPFS) can controller
11 - Conor Dooley <[email protected]>
14 - $ref: can-controller.yaml#
19 - items:
20 - const: microchip,pic64gx-can
21 - const: microchip,mpfs-can
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/i2c/
Dmicrochip,corei2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip MPFS I2C Controller
10 - Daire McNamara <[email protected]>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - items:
19 - enum:
20 - microchip,pic64gx-i2c
21 - microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
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/linux-6.14.4/drivers/reset/
Dreset-mpfs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PolarFire SoC (MPFS) Peripheral Clock Reset Controller
16 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/microchip,mpfs-clock.h>
18 #include <soc/microchip/mpfs.h>
22 * defines in the dt to make things easier to configure - so this is accounting
44 * Peripheral clock resets
54 reg = readl(rst->base); in mpfs_assert()
56 writel(reg, rst->base); in mpfs_assert()
71 reg = readl(rst->base); in mpfs_deassert()
[all …]
/linux-6.14.4/drivers/clk/microchip/
Dclk-mpfs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PolarFire SoC MSS/core complex clock control
5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/microchip,mpfs-clock.h>
12 #include <soc/microchip/mpfs.h>
34 * This clock ID is defined here, rather than the binding headers, as it is an
35 * internal clock only, and therefore has no consumers in other peripheral
84 * mpfs clk block while a software locked register is being written.
103 * The only two supported reference clock frequencies for the PolarFire SoC are
[all …]
Dclk-mpfs-ccc.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/microchip,mpfs-clock.h>
76 void __iomem *mult_addr = ccc_hw->base + ccc_hw->reg_offset; in mpfs_ccc_pll_recalc_rate()
77 void __iomem *ref_div_addr = ccc_hw->base + MPFS_CCC_REF_CR; in mpfs_ccc_pll_recalc_rate()
91 void __iomem *pll_cr_addr = ccc_hw->base + MPFS_CCC_PLL_CR; in mpfs_ccc_pll_get_parent()
167 char *name = devm_kasprintf(dev, GFP_KERNEL, "%s_out%u", parent->name, i); in mpfs_ccc_register_outputs()
170 return -ENOMEM; in mpfs_ccc_register_outputs()
172 out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0); in mpfs_ccc_register_outputs()
173 out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] + in mpfs_ccc_register_outputs()
[all …]
/linux-6.14.4/drivers/gpio/
Dgpio-mpfs.c1 // SPDX-License-Identifier: (GPL-2.0)
3 * Microchip PolarFire SoC (MPFS) GPIO controller driver
5 * Copyright (c) 2018-2024 Microchip Technology Inc. and its subsidiaries
61 regmap_update_bits(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index), in mpfs_gpio_direction_input()
71 regmap_update_bits(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index), in mpfs_gpio_direction_output()
73 regmap_update_bits(mpfs_gpio->regs, mpfs_gpio->offsets->outp, BIT(gpio_index), in mpfs_gpio_direction_output()
85 regmap_read(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index), &gpio_cfg); in mpfs_gpio_get_direction()
97 return regmap_test_bits(mpfs_gpio->regs, mpfs_gpio->offsets->outp, BIT(gpio_index)); in mpfs_gpio_get()
99 return regmap_test_bits(mpfs_gpio->regs, mpfs_gpio->offsets->inp, BIT(gpio_index)); in mpfs_gpio_get()
108 regmap_update_bits(mpfs_gpio->regs, mpfs_gpio->offsets->outp, BIT(gpio_index), in mpfs_gpio_set()
[all …]
/linux-6.14.4/drivers/usb/musb/
Dmpfs.c1 // SPDX-License-Identifier: GPL-2.0
3 * PolarFire SoC (MPFS) MUSB Glue Layer
5 * Copyright (c) 2020-2022 Microchip Corporation. All rights reserved.
11 #include <linux/dma-mapping.h>
61 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); in mpfs_musb_set_vbus()
64 musb->is_active = 1; in mpfs_musb_set_vbus()
65 musb->xceiv->otg->default_a = 1; in mpfs_musb_set_vbus()
66 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; in mpfs_musb_set_vbus()
70 musb->is_active = 0; in mpfs_musb_set_vbus()
73 * NOTE: skipping A_WAIT_VFALL -> A_IDLE and in mpfs_musb_set_vbus()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/mmc/
Dcdns,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <[email protected]>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - microchip,pic64gx-sd4hc
19 - socionext,uniphier-sd4hc
20 - const: cdns,sd4hc
[all …]
/linux-6.14.4/drivers/rtc/
Drtc-mpfs.c1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip MPFS RTC driver
5 * Copyright (c) 2021-2022 Microchip Corporation. All rights reserved.
65 ctrl = readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_start()
68 writel(ctrl, rtcdev->base + CONTROL_REG); in mpfs_rtc_start()
73 u32 val = readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq()
77 writel(val, rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq()
83 (void)readl(rtcdev->base + CONTROL_REG); in mpfs_rtc_clear_irq()
91 time = readl(rtcdev->base + DATETIME_LOWER_REG); in mpfs_rtc_readtime()
92 time |= ((u64)readl(rtcdev->base + DATETIME_UPPER_REG) & DATETIME_UPPER_MASK) << 32; in mpfs_rtc_readtime()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <[email protected]>
11 - Claudiu Beznea <[email protected]>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
[all …]
/linux-6.14.4/drivers/spi/
Dspi-microchip-core.c1 // SPDX-License-Identifier: (GPL-2.0)
5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries
107 u32 clk_gen; /* divider for spi output clock generated by the controller */
118 return readl(spi->regs + reg); in mchp_corespi_read()
123 writel(val, spi->regs + reg); in mchp_corespi_write()
145 spi->rx_len -= spi->n_bytes; in mchp_corespi_read_fifo()
147 if (!spi->rx_buf) in mchp_corespi_read_fifo()
150 if (spi->n_bytes == 4) in mchp_corespi_read_fifo()
151 *((u32 *)spi->rx_buf) = data; in mchp_corespi_read_fifo()
152 else if (spi->n_bytes == 2) in mchp_corespi_read_fifo()
[all …]
/linux-6.14.4/drivers/pci/controller/plda/
Dpcie-microchip-host.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved.
21 #include <linux/pci-ecam.h>
26 #include "pcie-plda.h"
300 struct plda_msi *msi = &port->plda.msi; in mc_pcie_enable_msi()
315 writel_relaxed(lower_32_bits(msi->vector_phy), in mc_pcie_enable_msi()
317 writel_relaxed(upper_32_bits(msi->vector_phy), in mc_pcie_enable_msi()
328 u32 reg = readl_relaxed(port->ctrl_base_addr + PCIE_EVENT_INT); in pcie_events()
340 u32 reg = readl_relaxed(port->ctrl_base_addr + SEC_ERROR_INT); in sec_errors()
352 u32 reg = readl_relaxed(port->ctrl_base_addr + DED_ERROR_INT); in ded_errors()
[all …]

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