Lines Matching +full:mpfs +full:- +full:clock
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <[email protected]>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - microchip,pic64gx-sd4hc
19 - socionext,uniphier-sd4hc
20 - const: cdns,sd4hc
37 # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
40 cdns,phy-input-delay-sd-highspeed:
41 description: Value of the delay in the input path for SD high-speed timing
46 cdns,phy-input-delay-legacy:
52 cdns,phy-input-delay-sd-uhs-sdr12:
58 cdns,phy-input-delay-sd-uhs-sdr25:
64 cdns,phy-input-delay-sd-uhs-sdr50:
70 cdns,phy-input-delay-sd-uhs-ddr50:
76 cdns,phy-input-delay-mmc-highspeed:
77 description: Value of the delay in the input path for MMC high-speed timing
82 cdns,phy-input-delay-mmc-ddr:
83 description: Value of the delay in the input path for eMMC high-speed DDR timing
85 # PHY DLL clock delays:
86 # Each delay property represents the fraction of the clock period.
93 cdns,phy-dll-delay-sdclk:
101 cdns,phy-dll-delay-sdclk-hsmmc:
109 cdns,phy-dll-delay-strobe:
118 - compatible
119 - reg
120 - interrupts
121 - clocks
124 - $ref: sdhci-common.yaml
125 - if:
129 const: amd,pensando-elba-sd4hc
134 - description: Host controller registers
135 - description: Elba byte-lane enable register for writes
137 - resets
146 - |
148 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
152 bus-width = <8>;
153 mmc-ddr-1_8v;
154 mmc-hs200-1_8v;
155 mmc-hs400-1_8v;
156 cdns,phy-dll-delay-sdclk = <0>;