Lines Matching +full:mpfs +full:- +full:clock
1 // SPDX-License-Identifier: (GPL-2.0)
5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries
107 u32 clk_gen; /* divider for spi output clock generated by the controller */
118 return readl(spi->regs + reg); in mchp_corespi_read()
123 writel(val, spi->regs + reg); in mchp_corespi_write()
145 spi->rx_len -= spi->n_bytes; in mchp_corespi_read_fifo()
147 if (!spi->rx_buf) in mchp_corespi_read_fifo()
150 if (spi->n_bytes == 4) in mchp_corespi_read_fifo()
151 *((u32 *)spi->rx_buf) = data; in mchp_corespi_read_fifo()
152 else if (spi->n_bytes == 2) in mchp_corespi_read_fifo()
153 *((u16 *)spi->rx_buf) = data; in mchp_corespi_read_fifo()
155 *spi->rx_buf = data; in mchp_corespi_read_fifo()
157 spi->rx_buf += spi->n_bytes; in mchp_corespi_read_fifo()
204 * would actually write zeros into the lower 16 bits on an mpfs250t-es, in mchp_corespi_set_xfer_size()
205 * despite documentation stating these bits were read-only. in mchp_corespi_set_xfer_size()
207 * on an mpfs250t-es and will be a NOP for the lower 16 bits on hardware in mchp_corespi_set_xfer_size()
227 if (spi->n_bytes == 4) in mchp_corespi_write_fifo()
228 word = spi->tx_buf ? *((u32 *)spi->tx_buf) : 0xaa; in mchp_corespi_write_fifo()
229 else if (spi->n_bytes == 2) in mchp_corespi_write_fifo()
230 word = spi->tx_buf ? *((u16 *)spi->tx_buf) : 0xaa; in mchp_corespi_write_fifo()
232 word = spi->tx_buf ? *spi->tx_buf : 0xaa; in mchp_corespi_write_fifo()
235 if (spi->tx_buf) in mchp_corespi_write_fifo()
236 spi->tx_buf += spi->n_bytes; in mchp_corespi_write_fifo()
240 spi->tx_len -= i * spi->n_bytes; in mchp_corespi_write_fifo()
268 struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller); in mchp_corespi_set_cs()
273 corespi->pending_slave_select = reg; in mchp_corespi_set_cs()
281 * doesn't see any spurious clock transitions whilst CS is enabled. in mchp_corespi_set_cs()
283 if (((spi->mode & SPI_CS_HIGH) == 0) == disable) in mchp_corespi_set_cs()
289 struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller); in mchp_corespi_setup()
300 if (spi->mode & SPI_CS_HIGH) { in mchp_corespi_setup()
303 corespi->pending_slave_select = reg; in mchp_corespi_setup()
335 /* max. possible spi clock rate is the apb clock rate */ in mchp_corespi_init()
336 clk_hz = clk_get_rate(spi->clk); in mchp_corespi_init()
337 host->max_speed_hz = clk_hz; in mchp_corespi_init()
346 spi->pending_slave_select = SSELOUT | SSEL_DIRECT; in mchp_corespi_init()
347 mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select); in mchp_corespi_init()
362 if (spi->clk_mode) in mchp_corespi_set_clk_gen()
367 mchp_corespi_write(spi, REG_CLK_GEN, spi->clk_gen); in mchp_corespi_set_clk_gen()
422 dev_err(&host->dev, in mchp_corespi_interrupt()
424 spi->rx_len, spi->tx_len); in mchp_corespi_interrupt()
430 dev_err(&host->dev, in mchp_corespi_interrupt()
432 spi->rx_len, spi->tx_len); in mchp_corespi_interrupt()
446 clk_hz = clk_get_rate(spi->clk); in mchp_corespi_calculate_clkgen()
448 return -EINVAL; in mchp_corespi_calculate_clkgen()
452 * There are two possible clock modes for the controller generated in mchp_corespi_calculate_clkgen()
453 * clock's division ratio: in mchp_corespi_calculate_clkgen()
459 * clk_gen is the register name for the clock divider on MPFS. in mchp_corespi_calculate_clkgen()
461 clk_gen = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1; in mchp_corespi_calculate_clkgen()
464 clk_gen = fls(clk_gen) - 1; in mchp_corespi_calculate_clkgen()
467 return -EINVAL; in mchp_corespi_calculate_clkgen()
469 spi->clk_mode = 0; in mchp_corespi_calculate_clkgen()
471 spi->clk_mode = 1; in mchp_corespi_calculate_clkgen()
474 spi->clk_gen = clk_gen; in mchp_corespi_calculate_clkgen()
485 ret = mchp_corespi_calculate_clkgen(spi, (unsigned long)xfer->speed_hz); in mchp_corespi_transfer_one()
487 dev_err(&host->dev, "failed to set clk_gen for target %u Hz\n", xfer->speed_hz); in mchp_corespi_transfer_one()
493 spi->tx_buf = xfer->tx_buf; in mchp_corespi_transfer_one()
494 spi->rx_buf = xfer->rx_buf; in mchp_corespi_transfer_one()
495 spi->tx_len = xfer->len; in mchp_corespi_transfer_one()
496 spi->rx_len = xfer->len; in mchp_corespi_transfer_one()
497 spi->n_bytes = roundup_pow_of_two(DIV_ROUND_UP(xfer->bits_per_word, BITS_PER_BYTE)); in mchp_corespi_transfer_one()
499 mchp_corespi_set_framesize(spi, xfer->bits_per_word); in mchp_corespi_transfer_one()
503 mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select); in mchp_corespi_transfer_one()
505 while (spi->tx_len) { in mchp_corespi_transfer_one()
506 int fifo_max = DIV_ROUND_UP(min(spi->tx_len, FIFO_DEPTH), spi->n_bytes); in mchp_corespi_transfer_one()
519 struct spi_device *spi_dev = msg->spi; in mchp_corespi_prepare_message()
522 mchp_corespi_set_mode(spi, spi_dev->mode); in mchp_corespi_prepare_message()
535 host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi)); in mchp_corespi_probe()
537 return dev_err_probe(&pdev->dev, -ENOMEM, in mchp_corespi_probe()
542 if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs)) in mchp_corespi_probe()
545 host->num_chipselect = num_cs; in mchp_corespi_probe()
546 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in mchp_corespi_probe()
547 host->use_gpio_descriptors = true; in mchp_corespi_probe()
548 host->setup = mchp_corespi_setup; in mchp_corespi_probe()
549 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); in mchp_corespi_probe()
550 host->transfer_one = mchp_corespi_transfer_one; in mchp_corespi_probe()
551 host->prepare_message = mchp_corespi_prepare_message; in mchp_corespi_probe()
552 host->set_cs = mchp_corespi_set_cs; in mchp_corespi_probe()
553 host->dev.of_node = pdev->dev.of_node; in mchp_corespi_probe()
557 spi->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in mchp_corespi_probe()
558 if (IS_ERR(spi->regs)) in mchp_corespi_probe()
559 return PTR_ERR(spi->regs); in mchp_corespi_probe()
561 spi->irq = platform_get_irq(pdev, 0); in mchp_corespi_probe()
562 if (spi->irq < 0) in mchp_corespi_probe()
563 return spi->irq; in mchp_corespi_probe()
565 ret = devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt, in mchp_corespi_probe()
566 IRQF_SHARED, dev_name(&pdev->dev), host); in mchp_corespi_probe()
568 return dev_err_probe(&pdev->dev, ret, in mchp_corespi_probe()
571 spi->clk = devm_clk_get_enabled(&pdev->dev, NULL); in mchp_corespi_probe()
572 if (IS_ERR(spi->clk)) in mchp_corespi_probe()
573 return dev_err_probe(&pdev->dev, PTR_ERR(spi->clk), in mchp_corespi_probe()
578 ret = devm_spi_register_controller(&pdev->dev, host); in mchp_corespi_probe()
581 return dev_err_probe(&pdev->dev, ret, in mchp_corespi_probe()
585 dev_info(&pdev->dev, "Registered SPI controller %d\n", host->bus_num); in mchp_corespi_probe()
607 { .compatible = "microchip,mpfs-spi" },
616 .name = "microchip-corespi",