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/aosp_15_r20/external/mesa3d/docs/relnotes/
H A D20.0.0.rst217 - pan/midgard: Optimize comparisions with similar operations
218 - pan/midgard: Move midgard_is_branch_unit to helpers
219 - pan/midgard: Optimize branches with inverted arguments
220 - pan/midgard: Fix midgard_compile.h includes
245 - pan/midgard: Remove OP_IS_STORE_VARY
246 - pan/midgard: Add a dummy source for loads
247 - pan/midgard: Refactor swizzles
248 - pan/midgard: Eliminate blank_alu_src
249 - pan/midgard: Use fp32 blend shaders
250 - pan/midgard: Validate tags when branching
[all …]
H A D19.3.0.rst246 - pan/midgard: Free liveness info
247 - pan/midgard: Allocate \`dependencies\` on stack
251 - pan/midgard: Represent unused nodes by ~0
252 - pan/midgard: Reorder bits check to fix 8-bit masks
253 - pan/midgard: Simplify contradictory check.
255 - pan/midgard: Mark fallthrough explicitly
265 - pan/midgard: Breakout texture reg select printer
266 - pan/midgard: Identify and disassemble indirect texture/sampler
270 - pan/midgard,bifrost: Expand nir_const_load_to_arr
273 - pan/midgard: Sketch static analysis to uniform count
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H A D19.1.0.rst379 - panfrost: Implement Midgard shader toolchain
408 - panfrost/midgard: Refactor tag lookahead code
409 - panfrost/midgard: Fix nested/chained if-else
411 - panfrost/midgard: Emit extended branches
419 - panfrost/midgard: Add fround(_even), ftrunc, ffma
424 - panfrost/midgard: Allow flt to run on most units
428 - panfrost/midgard: Don't force constant on VLUT
430 - panfrost/midgard: Promote smul to vmul
431 - panfrost/midgard: Preview for data hazards
456 - panfrost/midgard: Implement fpow
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H A D20.1.0.rst288 - pan/midgard: Break out one-src read_components
289 - pan/midgard: Implement mixed-type constant packing
291 - pan/midgard: Check for null consts
292 - pan/midgard: Remove unused variable
294 - pan/midgard: Fix scheduling issue with csel + render target reference
303 - pan/midgard: Track pressure when scheduling ld/st
304 - pan/midgard: Fix missing prefixes
305 - pan/midgard: Fix swizzles harder
306 - pan/midgard: Implement barriers
307 - pan/midgard: Allow jumping out of a shader
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H A D22.2.3.rst48 - panfrost: Use compute-based XFB on Midgard
49 - panfrost: Lower MAX_BLOCK_SIZE on Midgard
/aosp_15_r20/external/mesa3d/src/panfrost/ci/
H A Dgitlab-ci.yml1 .panfrost-midgard-rules:
26 - src/panfrost/midgard/**/*
29 .panfrost-midgard-manual-rules:
41 - src/panfrost/midgard/**/*
251 - .panfrost-midgard-rules
260 - .panfrost-midgard-manual-rules
269 - .panfrost-midgard-manual-rules
277 - .panfrost-midgard-manual-rules
281 - !reference [.panfrost-midgard-manual-rules, rules]
291 - .panfrost-midgard-rules
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/aosp_15_r20/external/mesa3d/src/panfrost/util/
H A Dpan_ir.h71 * Midgard can push at most 92 words, so this bound suffices. The Midgard
72 * compiler pushes less than this, as Midgard uses register-mapped uniforms
78 /* Architectural invariants (Midgard and Bifrost): UBO must be <= 2^16 bytes so
285 /* UBOs to push to Register Mapped Uniforms (Midgard) or Fast Access
296 struct midgard_shader_info midgard; member
398 * threads in a warp. For Midgard (including warping models), this returns 1, as
H A Dpan_lower_writeout.c28 /* Midgard can write all of color, depth and stencil in a single writeout
160 * Midgard */ in pan_nir_lower_zs_store()
/aosp_15_r20/external/mesa3d/src/gallium/drivers/panfrost/
H A Dpan_screen.c148 /* Compile side is done for Bifrost, Midgard TODO. Needs some kernel in panfrost_get_param()
236 * lifted on Midgard at a performance penalty. We conservatively in panfrost_get_param()
267 /* We would prefer varyings on Midgard, but proper sysvals on Bifrost */ in panfrost_get_param()
354 /* Mali supports GLES and QUADS. Midgard and v6 Bifrost in panfrost_get_param()
422 /* Used as ABI on Midgard */ in panfrost_get_shader_param()
461 /* The Bifrost compiler supports full 16-bit. Midgard could but int16 in panfrost_get_shader_param()
462 * support is untested, so restrict INT16 to Bifrost. Midgard in panfrost_get_shader_param()
783 * On Midgard, we don't allow more than 128 threads in each in panfrost_get_compute_param()
796 * On Midgard, with maximum register usage, the maximum in panfrost_get_compute_param()
H A Dpan_cmdstream.c124 /* CLAMP is only supported on Midgard, where it is broken for nearest in translate_tex_wrap()
1110 /* Even without any errata, Midgard represents "no mipmapping" as in panfrost_upload_sampler_sysval()
1151 * Midgard, we emulate the Bifrost path with some extra arithmetic in the
1989 /* Midgard needs vertexid/instanceid handled specially */ in panfrost_emit_vertex_data()
2226 /* On Midgard, these exist as real varyings. Later architectures use in pan_varying_present()
2569 /* Emitted with the FB descriptor on Midgard. */ in emit_tls()
2894 batch->tiler_ctx.midgard.vertex_count = batch->vertex_count; in panfrost_increase_vertex_count()
3883 if (!batch->tiler_ctx.midgard.polygon_list) { in batch_get_polygon_list()
3897 batch->tiler_ctx.midgard.polygon_list = batch->polygon_list_bo->ptr.gpu; in batch_get_polygon_list()
3915 batch->tiler_ctx.midgard.disable = !has_draws; in batch_get_polygon_list()
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H A Dpan_context.h51 #include "midgard/midgard_compile.h"
342 /* Midgard shaders that read the tilebuffer must be keyed for
465 * Descriptor at draw-time on Midgard
/aosp_15_r20/external/mesa3d/src/panfrost/lib/
H A Dpan_desc.c610 bool hierarchy = !tiler_ctx->midgard.no_hierarchical_tiling; in pan_emit_midgard_tiler()
612 assert(tiler_ctx->midgard.polygon_list); in pan_emit_midgard_tiler()
617 if (tiler_ctx->midgard.disable) { in pan_emit_midgard_tiler()
622 cfg.heap_start = tiler_ctx->midgard.polygon_list; in pan_emit_midgard_tiler()
623 cfg.heap_end = tiler_ctx->midgard.polygon_list; in pan_emit_midgard_tiler()
626 fb->width, fb->height, tiler_ctx->midgard.vertex_count, hierarchy); in pan_emit_midgard_tiler()
631 cfg.heap_start = tiler_ctx->midgard.heap.start; in pan_emit_midgard_tiler()
632 cfg.heap_end = cfg.heap_start + tiler_ctx->midgard.heap.size; in pan_emit_midgard_tiler()
635 cfg.polygon_list = tiler_ctx->midgard.polygon_list; in pan_emit_midgard_tiler()
H A Dpan_tiler.c39 * In practice, it's a bit more complicated than this. On Midgard chips with an
41 * tile size, but Midgard features "hierarchical tiling", where power-of-two
43 * level 1 (32x32), level 2 (64x64), per public information about Midgard's
94 * the earliest Midgard's SFBD through the latest Bifrost traces we have),
366 * is the implementation specific maximum in supported Midgard devices. in panfrost_choose_hierarchy_mask()
H A Dpan_scratch.c31 /* Midgard has a small register file, so shaders with high register pressure
46 * THREAD_TLS_ALLOC, and the worst-case value of 16 cores for Midgard per the
/aosp_15_r20/external/mesa3d/docs/drivers/
H A Dpanfrost.rst5 GPUs based on the Midgard and Bifrost microarchitectures. It is **conformant**
15 | T600, T620, T720 | Midgard (v4) | 2.0 | 2.1 |
17 | T760, T820, T830 | Midgard (v5) | 3.1 | 3.1 |
29 Other Midgard and Bifrost chips (e.g. G71) are not yet supported.
/aosp_15_r20/external/ComputeLibrary/src/core/
H A DGPUTarget.cpp144 return arm_compute::GPUTarget::MIDGARD; in get_midgard_target()
155 { GPUTarget::MIDGARD, "midgard" }, in string_from_target()
195 return GPUTarget::MIDGARD; in get_target_from_name()
/aosp_15_r20/external/mesa3d/docs/
H A Dsourcetree.rst88 - **panfrost** - Driver for ARM Mali Txxx (Midgard) and
172 - **midgard** - shader compiler for the Midgard generation GPUs
174 - **util** - shared code between Midgard and Bifrost shader compilers
/aosp_15_r20/external/mesa3d/src/panfrost/midgard/
H A Dmidgard_nir_algebraic.py38 # Midgard scales fsin/fcos arguments by pi.
72 # Size conversion is redundant to Midgard but needed for NIR, and writing this
79 # Midgard is able to type convert down by only one "step" per instruction; if
H A Dmidgard_compile.c45 #include "midgard.h"
470 /* Midgard image ops coordinates are 16-bit instead of 32-bit */ in midgard_preprocess_nir()
708 * in Midgard */ in emit_alu()
926 /* Midgard can perform certain modifiers on output of an ALU op */ in emit_alu()
968 * instruction for Midgard with the condition in emit_alu()
1991 /* Midgard doesn't seem to want special handling, though we do need to in emit_intrinsic()
2123 * Midgard wants the ref value in coord.z. in set_tex_coord()
2133 * Midgard wants the array index in coord.w. in set_tex_coord()
2536 /* Midgard supports two types of constants, embedded constants (128-bit) and
3104 /* Midgard prefetches instruction types, so during emission we in midgard_compile_shader_nir()
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H A Dmidgard_quirks.h31 /* Typed loads are broken on this Midgard GPU due to issue #10607 and #10632 and
102 unreachable("Invalid Midgard GPU ID"); in midgard_get_quirks()
/aosp_15_r20/external/mesa3d/src/panfrost/
H A Dmeson.build10 '.', 'include', 'shared', 'midgard', 'compiler', 'lib'
19 subdir('midgard') subdir
/aosp_15_r20/external/igt-gpu-tools/lib/
H A Dpanfrost-job.h505 * On midgard: Depth factor is exactly as passed to glPolygonOffset.
574 /* Blending information for the older non-MRT Midgard HW. Check for
584 * vertex shaders or the non-MRT case for Midgard (so the blob doesn't
818 * They also seem to be the same between Bifrost and Midgard. They're shared in
958 * gpu_scratchpad in the SFBD for Midgard, although it's slightly
984 * why this field is seperate (Midgard is Vulkan capable). Pointer to
/aosp_15_r20/external/ComputeLibrary/src/runtime/heuristics/dwc_native/
H A DClDWCNativeKernelConfig.h51 case GPUTarget::MIDGARD: in create()
52 // The heuristic for Midgard is the same as the one used for Arm Mali-G71 in create()
/aosp_15_r20/external/mesa3d/docs/drivers/panfrost/
H A Ddrm-shim.rst29 Mali-T720 Midgard (v4) 720
30 Mali-T860 Midgard (v5) 860
/aosp_15_r20/external/ComputeLibrary/src/gpu/cl/operators/
H A DClConv2d.cpp59 case arm_compute::GPUTarget::MIDGARD: in get_direct_conv_kernel_threshold_nhwc()
291 …arm_compute::GPUTarget::G72 || get_arch_from_target(gpu_target) == arm_compute::GPUTarget::MIDGARD) in get_convolution_method()
305 …rm_compute::GPUTarget::G72 || get_arch_from_target(gpu_target) == arm_compute::GPUTarget::MIDGARD)) in get_convolution_method()

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