Home
last modified time | relevance | path

Searched +full:ip +full:- +full:clock +full:- +full:frequency (Results 1 – 25 of 303) sorted by relevance

12345678910>>...13

/linux-6.14.4/Documentation/devicetree/bindings/i2c/
Dopencores,i2c-ocores.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Korsgaard <[email protected]>
11 - Andrew Lunn <[email protected]>
14 - $ref: /schemas/i2c/i2c-controller.yaml#
19 - items:
20 - enum:
21 - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
[all …]
Dmicrochip,corei2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daire McNamara <[email protected]>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - items:
19 - enum:
20 - microchip,pic64gx-i2c
21 - microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
22 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
[all …]
Di2c-demux-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-demux-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Pinctrl-based I2C Bus Demultiplexer
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
16 IP core at runtime which may have a better feature set for a given task than
17 another I2C IP core on the SoC. The most simple example is to fall back to
19 internal IP core.
21 +-------------------------------+
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/media/
Dnxp,imx-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <[email protected]>
11 - Laurent Pinchart <[email protected]>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
15 receiver IP core named CSIS. The IP core originates from Samsung, and may be
[all …]
Dsamsung,exynos4210-fimc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/samsung,exynos4210-fimc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <[email protected]>
11 - Sylwester Nawrocki <[email protected]>
15 fimc<n>, where <n> is an integer specifying the IP block instance.
20 - samsung,exynos4210-fimc
21 - samsung,exynos4212-fimc
22 - samsung,s5pv210-fimc
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/
Dxilinx.txt1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
10 Each IP-core has a set of parameters which the FPGA designer can use to
14 device drivers how the IP cores are configured, but it requires the kernel
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
[all …]
/linux-6.14.4/drivers/clk/sophgo/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
2 # common clock support for SOPHGO SoC family.
5 tristate "Support for the Sophgo CV1800 series SoCs clock controller"
8 This driver supports clock controller of Sophgo CV18XX series SoC.
9 The driver require a 25MHz Oscillator to function generate clock.
10 It includes PLLs, common clock function and some vendor clock for
14 tristate "Sophgo SG2042 PLL clock support"
17 This driver supports the PLL clock controller on the
18 Sophgo SG2042 SoC. This clock IP uses three oscillators with
19 frequency of 25 MHz as input, which are used for Main/Fixed
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/clock/ti/
Ddra7-atl.txt1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
5 functional clock but can be configured to provide different clocks.
6 ATL can maintain a clock averages to some desired frequency based on the bws/aws
7 signals - can compensate the drift between the two ws signal.
12 Clock tree binding:
13 This binding uses the common clock binding[1].
14 To be able to integrate the ATL clocks with DT clock tree.
16 Since the clock instances are part of a single IP this binding is used as a node
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/can/
Dmpc5xxx-mscan.txt2 ------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
7 fsl,mpc5200-mscan nodes
8 -----------------------
9 In addition to the required compatible-, reg- and interrupt-properties, you can
10 also specify which clock source shall be used for the controller:
12 - fsl,mscan-clock-source : a string describing the clock source. Valid values
13 are: "ip" for ip bus clock
14 "ref" for reference clock (XTAL)
18 fsl,mpc5121-mscan nodes
[all …]
Dgrcan.txt3 The GRCAN and CRHCAN CAN controllers are available in the GRLIB VHDL IP core
12 - name : Should be "GAISLER_GRCAN", "01_03d", "GAISLER_GRHCAN" or "01_034"
14 - reg : Address and length of the register set for the device
16 - freq : Frequency of the external oscillator clock in Hz (the frequency of
19 - interrupts : Interrupt number for this device
23 - systemid : If not present or if the value of the least significant 16 bits
24 of this 32-bit property is smaller than GRCAN_TXBUG_SAFE_GRLIB_VERSION
27 For further information look in the documentation for the GLIB IP core library:
/linux-6.14.4/drivers/pwm/
Dpwm-tegra.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <[email protected]>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
15 * The PWM clock frequency is divided by 256 before subdividing it based
16 * on the programmable frequency division value to generate the required
[all …]
/linux-6.14.4/arch/arc/boot/dts/
Dhsdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
[all …]
/linux-6.14.4/arch/arm64/boot/dts/renesas/
Dr8a779f0-spider-cpu.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
15 compatible = "renesas,spider-cpu", "renesas,r8a779f0";
29 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
30 stdout-path = "serial0:1843200n8";
34 compatible = "gpio-leds";
36 led-7 {
40 function-enumerator = <7>;
43 led-8 {
[all …]
Dr8a779f4-s4sk.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Source for the R-Car S4 Starter Kit board
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
13 model = "R-Car S4 Starter Kit board";
29 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
30 stdout-path = "serial0:921600n8";
45 vcc_sdhi: regulator-vcc-sdhi {
46 compatible = "regulator-fixed";
47 regulator-name = "SDHI Vcc";
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/display/bridge/
Dsamsung,mipi-dsim.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <[email protected]>
11 - Jagan Teki <[email protected]>
12 - Marek Szyprowski <[email protected]>
21 - enum:
22 - samsung,exynos3250-mipi-dsi
23 - samsung,exynos4210-mipi-dsi
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/iio/dac/
Dadi,axi-dac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/dac/adi,axi-dac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI DAC IP core
10 - Nuno Sa <[email protected]>
13 Analog Devices Generic AXI DAC IP core for interfacing a DAC device
17 interface for the actual DAC, while this IP core will interface
18 to the data-lines of the DAC and handle the streaming of data from
27 - adi,axi-dac-9.1.b
[all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/lunarlake/
Dpipeline.json8 …"Counts the total number of instructions in which the instruction pointer (IP) of the processor is…
28 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address…
43 "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles",
54 …frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep…
60 …"BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_C…
72 …frequency may change from time to time due to power or thermal throttling. For this reason, this e…
77 "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles",
88 …frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency…
94 "BriefDescription": "Counts the number of unhalted reference clock cycles",
98 …T instruction. This event is not affected by core frequency changes and increments at a fixed freq…
[all …]
/linux-6.14.4/include/linux/clk/
Dti.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * TI clock drivers support
10 #include <linux/clk-provider.h>
14 * struct clk_omap_reg - OMAP register declaration
15 * @offset: offset from the master IP module base address
17 * @index: index of the master IP module
29 * struct dpll_data - DPLL registers and integration data
33 * @clk_bypass: struct clk_hw pointer to the clock's bypass clock input
34 * @clk_ref: struct clk_hw pointer to the clock's reference clock input
43 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/spi/
Drockchip-sfc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <[email protected]>
11 - Chris Morgan <[email protected]>
14 - $ref: spi-controller.yaml#
20 The rockchip sfc controller is a standalone IP with version register,
21 and the driver can handle all the feature difference inside the IP
32 - description: Bus Clock
[all …]
/linux-6.14.4/arch/arm/boot/dts/microchip/
Danimeo_ip.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * animeo_ip.dts - Device Tree file for Somfy Animeo IP Boards
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
8 /dts-v1/;
12 model = "Somfy Animeo IP";
13 compatible = "somfy,animeo-ip", "atmel,at91sam9260", "atmel,at91sam9";
26 stdout-path = &usart2;
35 clock-frequency = <32768>;
39 clock-frequency = <18432000>;
47 compatible = "atmel,tcb-timer";
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <[email protected]>
11 - Anup Patel <[email protected]>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dfsl,qoriq-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Clock Block on Freescale QorIQ Platforms
10 - Frank Li <[email protected]>
14 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
17 cores and peripheral IP blocks.
24 --------------- -------------
28 Clock Provider
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/ptp/
Dfsl,ptp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QorIQ 1588 timer based PTP clock
10 - Frank Li <[email protected]>
15 - enum:
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
19 - items:
[all …]
/linux-6.14.4/drivers/clk/xilinx/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
10 register set. This driver also configures the frequency based on the
11 clock information from the logicoreIP register set.
25 Support for the Xilinx Clocking Wizard IP core clock generator.
27 This driver supports the Xilinx clocking wizard programmable clock
/linux-6.14.4/Documentation/devicetree/bindings/clock/sifive/
Dfu540-prci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
11 - Paul Walmsley <[email protected]>
14 On the FU540 family of SoCs, most system-wide clock and reset integration
15 is via the PRCI IP block.
16 The clock consumer should specify the desired clock via the clock ID
17 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
[all …]

12345678910>>...13