1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung MIPI DSIM bridge controller
8
9maintainers:
10  - Inki Dae <[email protected]>
11  - Jagan Teki <[email protected]>
12  - Marek Szyprowski <[email protected]>
13
14description: |
15  Samsung MIPI DSIM bridge controller can be found it on Exynos
16  and i.MX8M Mini/Nano/Plus SoC's.
17
18properties:
19  compatible:
20    oneOf:
21      - enum:
22          - samsung,exynos3250-mipi-dsi
23          - samsung,exynos4210-mipi-dsi
24          - samsung,exynos5410-mipi-dsi
25          - samsung,exynos5422-mipi-dsi
26          - samsung,exynos5433-mipi-dsi
27          - fsl,imx8mm-mipi-dsim
28          - fsl,imx8mp-mipi-dsim
29      - items:
30          - enum:
31              - fsl,imx7d-mipi-dsim
32              - fsl,imx8mn-mipi-dsim
33          - const: fsl,imx8mm-mipi-dsim
34
35  reg:
36    maxItems: 1
37
38  interrupts:
39    maxItems: 1
40
41  '#address-cells':
42    const: 1
43
44  '#size-cells':
45    const: 0
46
47  clocks:
48    minItems: 2
49    maxItems: 5
50
51  clock-names:
52    minItems: 2
53    maxItems: 5
54
55  samsung,phy-type:
56    $ref: /schemas/types.yaml#/definitions/uint32
57    description: phandle to the samsung phy-type
58
59  power-domains:
60    maxItems: 1
61
62  samsung,power-domain:
63    $ref: /schemas/types.yaml#/definitions/phandle
64    description: phandle to the associated samsung power domain
65
66  vddcore-supply:
67    description: MIPI DSIM Core voltage supply (e.g. 1.1V)
68
69  vddio-supply:
70    description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
71
72  samsung,burst-clock-frequency:
73    $ref: /schemas/types.yaml#/definitions/uint32
74    description:
75      DSIM high speed burst mode frequency.  If absent,
76      the pixel clock from the attached device or bridge
77      will be used instead.
78
79  samsung,esc-clock-frequency:
80    $ref: /schemas/types.yaml#/definitions/uint32
81    description:
82      DSIM escape mode frequency.
83
84  samsung,pll-clock-frequency:
85    $ref: /schemas/types.yaml#/definitions/uint32
86    description:
87      DSIM oscillator clock frequency. If absent, the clock frequency
88      of sclk_mipi will be used instead.
89
90  phys:
91    maxItems: 1
92
93  phy-names:
94    const: dsim
95
96  ports:
97    $ref: /schemas/graph.yaml#/properties/ports
98
99    properties:
100      port@0:
101        $ref: /schemas/graph.yaml#/properties/port
102        description:
103          Input port node to receive pixel data from the
104          display controller. Exactly one endpoint must be
105          specified.
106
107      port@1:
108        $ref: /schemas/graph.yaml#/$defs/port-base
109        unevaluatedProperties: false
110        description:
111          DSI output port node to the panel or the next bridge
112          in the chain.
113
114        properties:
115          endpoint:
116            $ref: /schemas/media/video-interfaces.yaml#
117            unevaluatedProperties: false
118
119            properties:
120              data-lanes:
121                minItems: 1
122                maxItems: 4
123                uniqueItems: true
124                items:
125                  enum: [ 1, 2, 3, 4 ]
126
127              lane-polarities:
128                minItems: 1
129                maxItems: 5
130                description:
131                  The Samsung MIPI DSI IP requires that all the data lanes have
132                  the same polarity.
133
134            dependencies:
135              lane-polarities: [data-lanes]
136
137required:
138  - clock-names
139  - clocks
140  - compatible
141  - interrupts
142  - reg
143  - samsung,esc-clock-frequency
144
145allOf:
146  - $ref: ../dsi-controller.yaml#
147  - if:
148      properties:
149        compatible:
150          contains:
151            const: samsung,exynos5433-mipi-dsi
152
153    then:
154      properties:
155        clocks:
156          minItems: 5
157
158        clock-names:
159          items:
160            - const: bus_clk
161            - const: phyclk_mipidphy0_bitclkdiv8
162            - const: phyclk_mipidphy0_rxclkesc0
163            - const: sclk_rgb_vclk_to_dsim0
164            - const: sclk_mipi
165
166        ports:
167          required:
168            - port@0
169
170      required:
171        - ports
172        - vddcore-supply
173        - vddio-supply
174
175  - if:
176      properties:
177        compatible:
178          contains:
179            const: samsung,exynos5410-mipi-dsi
180
181    then:
182      properties:
183        clocks:
184          minItems: 2
185
186        clock-names:
187          items:
188            - const: bus_clk
189            - const: pll_clk
190
191      required:
192        - vddcore-supply
193        - vddio-supply
194
195  - if:
196      properties:
197        compatible:
198          contains:
199            const: samsung,exynos4210-mipi-dsi
200
201    then:
202      properties:
203        clocks:
204          minItems: 2
205
206        clock-names:
207          items:
208            - const: bus_clk
209            - const: sclk_mipi
210
211      required:
212        - vddcore-supply
213        - vddio-supply
214
215  - if:
216      properties:
217        compatible:
218          contains:
219            const: samsung,exynos3250-mipi-dsi
220
221    then:
222      properties:
223        clocks:
224          minItems: 2
225
226        clock-names:
227          items:
228            - const: bus_clk
229            - const: pll_clk
230
231      required:
232        - vddcore-supply
233        - vddio-supply
234        - samsung,phy-type
235
236additionalProperties:
237  type: object
238
239examples:
240  - |
241    #include <dt-bindings/clock/exynos5433.h>
242    #include <dt-bindings/gpio/gpio.h>
243    #include <dt-bindings/interrupt-controller/arm-gic.h>
244
245    dsi@13900000 {
246        compatible = "samsung,exynos5433-mipi-dsi";
247        reg = <0x13900000 0xC0>;
248        interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
249        phys = <&mipi_phy 1>;
250        phy-names = "dsim";
251        clocks = <&cmu_disp CLK_PCLK_DSIM0>,
252                 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
253                 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
254                 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
255                 <&cmu_disp CLK_SCLK_DSIM0>;
256        clock-names = "bus_clk",
257                      "phyclk_mipidphy0_bitclkdiv8",
258                      "phyclk_mipidphy0_rxclkesc0",
259                      "sclk_rgb_vclk_to_dsim0",
260                      "sclk_mipi";
261        power-domains = <&pd_disp>;
262        vddcore-supply = <&ldo6_reg>;
263        vddio-supply = <&ldo7_reg>;
264        samsung,burst-clock-frequency = <512000000>;
265        samsung,esc-clock-frequency = <16000000>;
266        samsung,pll-clock-frequency = <24000000>;
267        pinctrl-names = "default";
268        pinctrl-0 = <&te_irq>;
269
270        ports {
271            #address-cells = <1>;
272            #size-cells = <0>;
273
274            port@0 {
275                reg = <0>;
276
277                dsi_to_mic: endpoint {
278                    remote-endpoint = <&mic_to_dsi>;
279                };
280            };
281        };
282    };
283