1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: SiFive Core Local Interruptor
8
9maintainers:
10  - Palmer Dabbelt <[email protected]>
11  - Anup Patel <[email protected]>
12
13description:
14  SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15  Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16  interrupts. It directly connects to the timer and inter-processor interrupt
17  lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
18  interrupt controller is the parent interrupt controller for CLINT device.
19  The clock frequency of CLINT is specified via "timebase-frequency" DT
20  property of "/cpus" DT node. The "timebase-frequency" DT property is
21  described in Documentation/devicetree/bindings/riscv/cpus.yaml
22
23  T-Head C906/C910 CPU cores include an implementation of CLINT too, however
24  their implementation lacks a memory-mapped MTIME register, thus not
25  compatible with SiFive ones.
26
27properties:
28  compatible:
29    oneOf:
30      - items:
31          - enum:
32              - canaan,k210-clint       # Canaan Kendryte K210
33              - sifive,fu540-c000-clint # SiFive FU540
34              - spacemit,k1-clint       # SpacemiT K1
35              - starfive,jh7100-clint   # StarFive JH7100
36              - starfive,jh7110-clint   # StarFive JH7110
37              - starfive,jh8100-clint   # StarFive JH8100
38          - const: sifive,clint0        # SiFive CLINT v0 IP block
39      - items:
40          - enum:
41              - allwinner,sun20i-d1-clint
42              - sophgo,cv1800b-clint
43              - sophgo,cv1812h-clint
44              - sophgo,sg2002-clint
45              - thead,th1520-clint
46          - const: thead,c900-clint
47      - items:
48          - const: sifive,clint0
49          - const: riscv,clint0
50        deprecated: true
51        description: For the QEMU virt machine only
52
53    description:
54      Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
55      when compatible with a SiFive CLINT.  Please refer to
56      sifive-blocks-ip-versioning.txt for details regarding the latter.
57
58  reg:
59    maxItems: 1
60
61  interrupts-extended:
62    minItems: 1
63    maxItems: 4095
64
65additionalProperties: false
66
67required:
68  - compatible
69  - reg
70  - interrupts-extended
71
72examples:
73  - |
74    timer@2000000 {
75      compatible = "sifive,fu540-c000-clint", "sifive,clint0";
76      interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
77                            <&cpu2intc 3>, <&cpu2intc 7>,
78                            <&cpu3intc 3>, <&cpu3intc 7>,
79                            <&cpu4intc 3>, <&cpu4intc 7>;
80       reg = <0x2000000 0x10000>;
81    };
82...
83