Home
last modified time | relevance | path

Searched +full:full +full:- +full:bit (Results 1 – 25 of 1116) sorted by relevance

12345678910>>...45

/linux-6.14.4/drivers/net/phy/
Dphy-core.c1 // SPDX-License-Identifier: GPL-2.0+
10 * phy_speed_to_str - Return a string representing the PHY link speed
57 return "Unsupported (update phy-core.c)"; in phy_speed_to_str()
63 * phy_duplex_to_str - Return string describing the duplex
72 return "Full"; in phy_duplex_to_str()
75 return "Unsupported (update phy-core.c)"; in phy_duplex_to_str()
80 * phy_rate_matching_to_str - Return a string describing the rate matching
94 return "open-loop"; in phy_rate_matching_to_str()
96 return "Unsupported (update phy-core.c)"; in phy_rate_matching_to_str()
101 * phy_interface_num_ports - Return the number of links that can be carried by
[all …]
/linux-6.14.4/drivers/acpi/acpica/
Dutmath.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: utmath - Integer math support routines
14 /* Structures used only for 64-bit divide */
22 u64 full; member
28 * Optional support for 64-bit double-precision integer multiply and shift.
29 * This code is configurable and is implemented in order to support 32-bit
30 * kernel environments where a 64-bit double-precision math library is not
39 * PARAMETERS: multiplicand - 64-bit multiplicand
40 * multiplier - 32-bit multiplier
41 * out_product - Pointer to where the product is returned
[all …]
/linux-6.14.4/drivers/comedi/drivers/
Djr3_pci.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * is 16 bits, but aligned on a 32 bit PCI boundary
31 * two-byte words.
42 * Channels 1-6 contain the coupled force data Fx through Mz. Channel
43 * 7 contains the sensor's calibration data. The use of channels 8-15
70 * the full scales.
84 * which axes to use in computing the vectors. Each bit signifies
85 * selection of a single axis. The V1x axis bit corresponds to a hex
86 * value of 0x0001 and the V2z bit corresponds to a hex value of
91 * calculated. Setting the changeV1 bit or the changeV2 bit will
[all …]
/linux-6.14.4/drivers/net/ethernet/sunplus/
Dspl2sw_define.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define MAX_NETDEV_NUM 2 /* Maximum # of net-device */
12 #define MAC_INT_DAISY_MODE_CHG BIT(31) /* Daisy Mode Change */
13 #define MAC_INT_IP_CHKSUM_ERR BIT(23) /* IP Checksum Append Error */
14 #define MAC_INT_WDOG_TIMER1_EXP BIT(22) /* Watchdog Timer1 Expired */
15 #define MAC_INT_WDOG_TIMER0_EXP BIT(21) /* Watchdog Timer0 Expired */
16 #define MAC_INT_INTRUDER_ALERT BIT(20) /* Atruder Alert */
17 #define MAC_INT_PORT_ST_CHG BIT(19) /* Port Status Change */
18 #define MAC_INT_BC_STORM BIT(18) /* Broad Cast Storm */
19 #define MAC_INT_MUST_DROP_LAN BIT(17) /* Global Queue Exhausted */
[all …]
/linux-6.14.4/include/linux/
Dcnt32_to_63.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Extend a 32-bit counter to 63 bits
31 * cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter
35 * a relatively short period making wrap-arounds rather frequent. This
36 * is a problem when implementing sched_clock() for example, where a 64-bit
37 * non-wrapping monotonic value is expected to be returned.
39 * To overcome that limitation, let's extend a 32-bit counter to 63 bits
41 * by the hardware while bits 32 to 62 are stored in memory. The top bit in
42 * memory is used to synchronize with the hardware clock half-period. When
43 * the top bit of both counters (hardware and in memory) differ then the
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/dma/stm32/
Dst,stm32-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
17 3. A 32bit mask specifying the DMA channel configuration which are device
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
[all …]
/linux-6.14.4/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
Dcore-imp-def.json93 … "PublicDescription": "Count predict pipe stalls due to speculative return address predictor full",
96 … "BriefDescription": "Count predict pipe stalls due to speculative return address predictor full"
99 "PublicDescription": "Macro-ops speculatively decoded",
102 "BriefDescription": "Macro-ops speculatively decoded"
117 "PublicDescription": "ETM extout bit 0",
120 "BriefDescription": "ETM extout bit 0"
123 "PublicDescription": "ETM extout bit 1",
126 "BriefDescription": "ETM extout bit 1"
129 "PublicDescription": "ETM extout bit 2",
132 "BriefDescription": "ETM extout bit 2"
[all …]
/linux-6.14.4/drivers/net/ethernet/stmicro/stmmac/
Ddwmac1000.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
26 #define GMAC_INT_STATUS_PMT BIT(3)
27 #define GMAC_INT_STATUS_MMCIS BIT(4)
28 #define GMAC_INT_STATUS_MMCRIS BIT(5)
29 #define GMAC_INT_STATUS_MMCTIS BIT(6)
30 #define GMAC_INT_STATUS_MMCCSUM BIT(7)
31 #define GMAC_INT_STATUS_TSTAMP BIT(9)
32 #define GMAC_INT_STATUS_LPIIS BIT(10)
[all …]
/linux-6.14.4/tools/perf/pmu-events/arch/arm64/ampere/ampereone/
Dcore-imp-def.json93 … "PublicDescription": "Count predict pipe stalls due to speculative return address predictor full",
96 … "BriefDescription": "Count predict pipe stalls due to speculative return address predictor full"
99 "PublicDescription": "Macro-ops speculatively decoded",
102 "BriefDescription": "Macro-ops speculatively decoded"
117 "PublicDescription": "ETM extout bit 0",
120 "BriefDescription": "ETM extout bit 0"
123 "PublicDescription": "ETM extout bit 1",
126 "BriefDescription": "ETM extout bit 1"
129 "PublicDescription": "ETM extout bit 2",
132 "BriefDescription": "ETM extout bit 2"
[all …]
/linux-6.14.4/include/asm-generic/bitops/
Dinstrumented-atomic.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * This file provides wrappers with sanitizer instrumentation for atomic bit
8 * the below bit operations with an arch_ prefix (e.g. arch_set_bit(),
17 * set_bit - Atomically set a bit in memory
18 * @nr: the bit to set
24 * restricted to acting on a single-word quantity.
33 * clear_bit - Clears a bit in memory
34 * @nr: Bit to clear
46 * change_bit - Toggle a bit in memory
47 * @nr: Bit to change
[all …]
/linux-6.14.4/drivers/power/supply/
Dcpcap-battery.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * Copyright (C) 2009-2010 Motorola, Inc.
23 #include <linux/nvmem-consumer.h>
28 #include <linux/mfd/motorola-cpcap.h>
31 * Register bit defines for CPCAP_REG_BPEOL. Some of these seem to
32 * map to MC13783UG.pdf "Table 5-19. Register 13, Power Control 0"
36 #define CPCAP_REG_BPEOL_BIT_EOL9 BIT(9) /* Set for EOL irq */
37 #define CPCAP_REG_BPEOL_BIT_EOL8 BIT(8) /* Set for EOL irq */
38 #define CPCAP_REG_BPEOL_BIT_UNKNOWN7 BIT(7)
39 #define CPCAP_REG_BPEOL_BIT_UNKNOWN6 BIT(6)
[all …]
/linux-6.14.4/drivers/mmc/host/
Dsdhci-uhs2.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 #define SDHCI_UHS2_TRNS_DMA BIT(0)
30 #define SDHCI_UHS2_TRNS_BLK_CNT_EN BIT(1)
31 #define SDHCI_UHS2_TRNS_DATA_TRNS_WRT BIT(4)
32 #define SDHCI_UHS2_TRNS_BLK_BYTE_MODE BIT(5)
33 #define SDHCI_UHS2_TRNS_RES_R5 BIT(6)
34 #define SDHCI_UHS2_TRNS_RES_ERR_CHECK_EN BIT(7)
35 #define SDHCI_UHS2_TRNS_RES_INT_DIS BIT(8)
36 #define SDHCI_UHS2_TRNS_WAIT_EBSY BIT(14)
37 #define SDHCI_UHS2_TRNS_2L_HD BIT(15)
[all …]
/linux-6.14.4/drivers/staging/gpib/include/
Dtnt4882_registers.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 // register number for auxiliary command register when swap bit is set (9914 mode)
49 /* TURBO-488 registers bit definitions */
62 /* CFG -- Configuration Register (write only) */
65 * (tnt4882 one-chip and newer only?)
75 TNT_B_16BIT = (1 << 0), /* 1=FIFO is 16-bit register, 0=8-bit */
78 /* CMDR -- Command Register */
80 CLRSC = 0x2, /* clear the system controller bit */
81 SETSC = 0x3, /* set the system controller bit */
89 /* HSSEL -- handshake select register (write only) */
[all …]
/linux-6.14.4/drivers/scsi/
Daha1542.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define STST BIT(7) /* Self Test in Progress */
11 #define DIAGF BIT(6) /* Internal Diagnostic Failure */
12 #define INIT BIT(5) /* Mailbox Initialization Required */
13 #define IDLE BIT(4) /* SCSI Host Adapter Idle */
14 #define CDF BIT(3) /* Command/Data Out Port Full */
15 #define DF BIT(2) /* Data In Port Full */
16 /* BIT(1) is reserved */
17 #define INVDCMD BIT(0) /* Invalid H A Command */
21 #define ANYINTR BIT(7) /* Any Interrupt */
[all …]
/linux-6.14.4/arch/x86/include/asm/
Dperf_event.h1 /* SPDX-License-Identifier: GPL-2.0 */
145 /* Steal the highest bit of pebs_data_cfg for SW usage */
159 unsigned int full; member
172 unsigned int full; member
183 unsigned int full; member
196 /* Counters Sub-Leaf */
198 /* Auto Counter Reload Sub-Leaf */
200 /* Events Sub-Leaf */
204 unsigned int full; member
211 /* EQ-bit Supported */
[all …]
/linux-6.14.4/Documentation/admin-guide/hw-vuln/
Dtsx_async_abort.rst1 .. SPDX-License-Identifier: GPL-2.0
3 TAA - TSX Asynchronous Abort
11 -------------------
14 Transactional Synchronization Extensions (TSX) when the TAA_NO bit (bit 8)
15 is 0 in the IA32_ARCH_CAPABILITIES MSR. On processors where the MDS_NO bit
16 (bit 5) is 0 in the IA32_ARCH_CAPABILITIES MSR, the existing MDS mitigations
23 ------------
28 CVE-2019-11135 TAA TSX Asynchronous Abort (TAA) condition on some
36 -------
43 hardware transactional memory support to improve performance of multi-threaded
[all …]
/linux-6.14.4/Documentation/networking/device_drivers/can/
Dcan327.rst1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
7 --------
14 -----------
26 -------------
29 into full fledged (as far as possible) CAN interfaces.
33 order to fake full-duplex operation.
36 enough to implement simple request-response protocols (such as OBD II),
50 -----------
59 ----------------------------------
68 --debug \
[all …]
/linux-6.14.4/tools/testing/selftests/kvm/
Ddirty_log_test.c1 // SPDX-License-Identifier: GPL-2.0
45 # define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7)
144 * is the only place that we'll guarantee both "dirty bit" and "dirty data"
146 * after setting dirty bit but before the data is written.
151 * ring-full event. It should only be read until a sem_wait() of
157 * tricky case when the ring just got full, kvm will do userspace exit due to
158 * ring full. When that happens, the very last PFN is set but actually the
160 * we found that the dirty ring is full, refused to continue the vcpu, and
164 * bit, because it's a redundant bit, and when the write happens later the bit
209 while (ret == -1 && errno == EINTR); in sem_wait_until()
[all …]
/linux-6.14.4/arch/m68k/include/asm/
Dmcfuart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfuart.h -- ColdFire internal UART support defines.
7 * (C) Copyright 1999-2003, Greg Ungerer ([email protected])
52 #define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
53 #define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
57 * Define bit flags in Mode Register 1 (MR1).
60 #define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
77 * Define bit flags in Mode Register 2 (MR2).
85 #define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */
90 * Define bit flags in Status Register (USR).
[all …]
/linux-6.14.4/drivers/pwm/
Dpwm-pca9685.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for PCA9685 16-channel 12-bit PWM LED controller
8 * based on the pwm-twl-led.c driver
59 #define LED_FULL BIT(4)
60 #define MODE1_ALLCALL BIT(0)
61 #define MODE1_SUB3 BIT(1)
62 #define MODE1_SUB2 BIT(2)
63 #define MODE1_SUB1 BIT(3)
64 #define MODE1_SLEEP BIT(4)
65 #define MODE2_INVRT BIT(4)
[all …]
/linux-6.14.4/drivers/spi/
Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
35 * to have a CS go down over the full transfer
46 #define SPICC_ENABLE BIT(0)
47 #define SPICC_MODE_MASTER BIT(1)
48 #define SPICC_XCH BIT(2)
49 #define SPICC_SMC BIT(3)
[all …]
/linux-6.14.4/arch/mips/include/asm/
Dcmpxchg.h6 * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
20 * - Get an error at compile-time due to __compiletime_error, if supported by
25 * - Get an error at link-time due to the call to the missing function.
44 " " __SYNC(full, loongson3_war) " \n" \
122 " " __SYNC(full, loongson3_war) " \n" \
131 "2: " __SYNC(full, loongson3_war) " \n" \
223 # include <asm-generic/cmpxchg-local.h>
236 * The assembly below has to combine 32 bit values into a 64 bit in __cmpxchg64()
237 * register, and split 64 bit values from one register into two. If we in __cmpxchg64()
240 * most significant 32 bits of the 64 bit values we're using. In order in __cmpxchg64()
[all …]
/linux-6.14.4/include/uapi/linux/
Dmii.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * linux/mii.h: definitions for MII-compatible transceivers
23 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
24 #define MII_STAT1000 0x0a /* 1000BASE-T status */
30 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
44 #define BMCR_FULLDPLX 0x0100 /* Full duplex */
55 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
58 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
60 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
63 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
[all …]
/linux-6.14.4/Documentation/hwmon/
Dvt1211.rst10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
31 UCH1, bit 1 maps to UCH2 and so on. Setting a bit to 1
33 setting a bit to 0 enables the voltage input.
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
[all …]
/linux-6.14.4/drivers/hwtracing/coresight/
Dcoresight-tmc.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/dma-mapping.h>
45 /* TMC_CTL - 0x020 */
46 #define TMC_CTL_CAPT_EN BIT(0)
47 /* TMC_STS - 0x00C */
49 #define TMC_STS_FULL BIT(0)
50 #define TMC_STS_TRIGGERED BIT(1)
51 #define TMC_STS_MEMERR BIT(5)
53 * TMC_AXICTL - 0x110
55 * TMC AXICTL format for SoC-400
[all …]

12345678910>>...45