Lines Matching +full:full +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
26 #define GMAC_INT_STATUS_PMT BIT(3)
27 #define GMAC_INT_STATUS_MMCIS BIT(4)
28 #define GMAC_INT_STATUS_MMCRIS BIT(5)
29 #define GMAC_INT_STATUS_MMCTIS BIT(6)
30 #define GMAC_INT_STATUS_MMCCSUM BIT(7)
31 #define GMAC_INT_STATUS_TSTAMP BIT(9)
32 #define GMAC_INT_STATUS_LPIIS BIT(10)
36 #define GMAC_INT_DISABLE_RGMII BIT(0)
37 #define GMAC_INT_DISABLE_PCSLINK BIT(1)
38 #define GMAC_INT_DISABLE_PCSAN BIT(2)
39 #define GMAC_INT_DISABLE_PMT BIT(3)
40 #define GMAC_INT_DISABLE_TIMESTAMP BIT(9)
79 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
81 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
89 #define GMAC_RGSMIIIS_LNKMODE BIT(0)
92 #define GMAC_RGSMIIIS_LNKSTS BIT(3)
93 #define GMAC_RGSMIIIS_JABTO BIT(4)
94 #define GMAC_RGSMIIIS_FALSECARDET BIT(5)
95 #define GMAC_RGSMIIIS_SMIDRXS BIT(16)
119 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
157 #define GMAC_DEBUG_TXSTSFSTS BIT(25) /* MTL TxStatus FIFO Full Status */
158 #define GMAC_DEBUG_TXFSTS BIT(24) /* MTL Tx FIFO Not Empty Status */
159 #define GMAC_DEBUG_TWCSTS BIT(22) /* MTL Tx FIFO Write Controller */
167 #define GMAC_DEBUG_TXPAUSED BIT(19) /* MAC Transmitter in PAUSE */
176 #define GMAC_DEBUG_TPESTS BIT(16)
177 #define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
189 #define GMAC_DEBUG_RWCSTS BIT(4) /* MTL Rx FIFO Write Controller Active */
194 #define GMAC_DEBUG_RPESTS BIT(0)
196 /*--- DMA BLOCK defines ---*/
214 #define DMA_BUS_MODE_RPBL_MASK 0x007e0000 /* Rx-Programmable Burst Len */
277 * Bit Field
278 * 0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled)
279 * 0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled)
280 * 0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled)
281 * 0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled)
282 * 1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled)
283 * 1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled)
284 * 1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled)
285 * 1,11 - Reserved
290 * Be sure that bit 3 in GMAC Register 6 is set for Unicast Pause frame
294 * Be sure that DZPA (bit 7 in Flow Control Register, GMAC Register 6),
337 #define GMAC_PTP_TCR_ATSFC BIT(24)
338 #define GMAC_PTP_TCR_ATSEN0 BIT(25)