Lines Matching +full:full +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 #define SDHCI_UHS2_TRNS_DMA BIT(0)
30 #define SDHCI_UHS2_TRNS_BLK_CNT_EN BIT(1)
31 #define SDHCI_UHS2_TRNS_DATA_TRNS_WRT BIT(4)
32 #define SDHCI_UHS2_TRNS_BLK_BYTE_MODE BIT(5)
33 #define SDHCI_UHS2_TRNS_RES_R5 BIT(6)
34 #define SDHCI_UHS2_TRNS_RES_ERR_CHECK_EN BIT(7)
35 #define SDHCI_UHS2_TRNS_RES_INT_DIS BIT(8)
36 #define SDHCI_UHS2_TRNS_WAIT_EBSY BIT(14)
37 #define SDHCI_UHS2_TRNS_2L_HD BIT(15)
40 #define SDHCI_UHS2_CMD_SUB_CMD BIT(2)
41 #define SDHCI_UHS2_CMD_DATA BIT(5)
42 #define SDHCI_UHS2_CMD_TRNS_ABORT BIT(6)
43 #define SDHCI_UHS2_CMD_CMD12 BIT(7)
62 #define SDHCI_UHS2_DEV_SEL_INT_MSG_EN BIT(7)
67 #define SDHCI_UHS2_SW_RESET_FULL BIT(0)
68 #define SDHCI_UHS2_SW_RESET_SD BIT(1)
76 #define SDHCI_UHS2_INT_HEADER_ERR BIT(0)
77 #define SDHCI_UHS2_INT_RES_ERR BIT(1)
78 #define SDHCI_UHS2_INT_RETRY_EXP BIT(2)
79 #define SDHCI_UHS2_INT_CRC BIT(3)
80 #define SDHCI_UHS2_INT_FRAME_ERR BIT(4)
81 #define SDHCI_UHS2_INT_TID_ERR BIT(5)
82 #define SDHCI_UHS2_INT_UNRECOVER BIT(7)
83 #define SDHCI_UHS2_INT_EBUSY_ERR BIT(8)
84 #define SDHCI_UHS2_INT_ADMA_ERROR BIT(15)
85 #define SDHCI_UHS2_INT_CMD_TIMEOUT BIT(16)
86 #define SDHCI_UHS2_INT_DEADLOCK_TIMEOUT BIT(17)
87 #define SDHCI_UHS2_INT_VENDOR_ERR BIT(27)
116 #define SDHCI_UHS2_GEN_SETTINGS_POWER_LOW BIT(0)
119 #define SDHCI_UHS2_2D1U_FD 0x2 /* 3 lanes, 2 down, 1 up, full duplex */
120 #define SDHCI_UHS2_1D2U_FD 0x3 /* 3 lanes, 1 down, 2 up, full duplex */
121 #define SDHCI_UHS2_2D2U_FD 0x4 /* 4 lanes, 2 down, 2 up, full duplex */
123 #define SDHCI_UHS2_PHY_SET_SPEED_B BIT(6)
124 #define SDHCI_UHS2_PHY_HIBERNATE_EN BIT(12)
142 #define SDHCI_UHS2_CAPS_ADDR_64 BIT(14)
143 #define SDHCI_UHS2_CAPS_BOOT BIT(15)