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/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dqcom,mmcc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeffrey Hugo <[email protected]>
11 - Taniya Das <[email protected]>
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8226
23 - qcom,mmcc-msm8660
24 - qcom,mmcc-msm8960
[all …]
/linux-6.14.4/drivers/gpu/drm/hisilicon/kirin/
Ddw_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DesignWare MIPI DSI Host Controller v1.02 driver
6 * Copyright (c) 2014-2016 HiSilicon Limited.
89 struct mipi_phy_params phy; member
98 struct dw_dsi dsi; member
122 static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy) in dsi_calc_phy_rate() argument
152 phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; in dsi_calc_phy_rate()
153 phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; in dsi_calc_phy_rate()
155 if (phy->hstx_ckg_sel <= 7 && in dsi_calc_phy_rate()
156 phy->hstx_ckg_sel >= 4) in dsi_calc_phy_rate()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/display/msm/
Ddsi-phy-7nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI 7nm PHY
10 - Jonathan Marek <[email protected]>
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-7nm
19 - qcom,dsi-phy-7nm-8150
20 - qcom,sc7280-dsi-phy-7nm
[all …]
Ddsi-phy-28nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI 28nm PHY
10 - Krishna Manikandan <[email protected]>
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-28nm-8226
19 - qcom,dsi-phy-28nm-8937
20 - qcom,dsi-phy-28nm-8960
[all …]
Ddsi-phy-14nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI 14nm PHY
10 - Krishna Manikandan <[email protected]>
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-14nm
19 - qcom,dsi-phy-14nm-2290
20 - qcom,dsi-phy-14nm-660
[all …]
Ddsi-phy-10nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI 10nm PHY
10 - Krishna Manikandan <[email protected]>
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-10nm
19 - qcom,dsi-phy-10nm-8998
23 - description: dsi phy register set
[all …]
Ddsi-phy-20nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI 20nm PHY
10 - Krishna Manikandan <[email protected]>
13 - $ref: dsi-phy-common.yaml#
17 const: qcom,dsi-phy-20nm
21 - description: dsi pll register set
22 - description: dsi phy register set
[all …]
Dqcom,mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <[email protected]>
11 - Rob Clark <[email protected]>
15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
19 pattern: "^display-subsystem@[0-9a-f]+$"
23 - qcom,mdss
29 reg-names:
32 - const: mdss_phys
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Dqcom,sdm845-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <[email protected]>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sdm845-mdss
25 - description: Display AHB clock from gcc
26 - description: Display core clock
[all …]
Dqcom,msm8998-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <[email protected]>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,msm8998-mdss
25 - description: Display AHB clock
26 - description: Display AXI clock
[all …]
Dqcom,sdm670-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm670-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Acayan <[email protected]>
13 SDM670 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14 like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sdm670-mdss
24 - description: Display AHB clock from gcc
[all …]
Dqcom,sm8650-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <[email protected]>
13 SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm8650-mdss
24 - description: Display AHB
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/linux-6.14.4/drivers/gpu/drm/rockchip/
Ddw-mipi-dsi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Chris Zhong <zyw@rock-chips.com>
6 * Nickey Yang <nickey.yang@rock-chips.com>
16 #include <linux/phy/phy.h>
41 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
93 #define INPUT_DIVIDER(val) (((val) - 1) & 0x7f)
96 #define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f)
97 #define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf)
255 int (*dphy_rx_init)(struct phy *phy);
256 int (*dphy_rx_power_on)(struct phy *phy);
[all …]
/linux-6.14.4/drivers/gpu/drm/bridge/
Dnwl-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX8 NWL MIPI DSI host driver
15 #include <linux/media-bus-format.h>
19 #include <linux/phy/phy.h>
34 #include "nwl-dsi.h"
36 #define DRV_NAME "nwl-dsi"
70 struct phy *phy; member
77 * The DSI host controller needs this reset sequence according to NWL:
78 * 1. Deassert pclk reset to get access to DSI regs
79 * 2. Configure DSI Host and DPHY and enable DPHY
[all …]
/linux-6.14.4/drivers/gpu/drm/msm/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
64 depends on $(success,$(PYTHON3) -c "import lxml")
66 Validate XML files with register definitions against rules-fd schema.
115 bool "Enable DSI support in MSM DRM driver"
122 Choose this option if you have a need for MIPI DSI connector
126 bool "Enable DSI 28nm PHY driver in MSM DRM"
130 Choose this option if the 28nm DSI PHY is used on the platform.
133 bool "Enable DSI 20nm PHY driver in MSM DRM"
137 Choose this option if the 20nm DSI PHY is used on the platform.
140 bool "Enable DSI 28nm 8960 PHY driver in MSM DRM"
[all …]
/linux-6.14.4/drivers/phy/mediatek/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the phy drivers.
6 obj-$(CONFIG_PHY_MTK_DP) += phy-mtk-dp.o
7 obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
8 obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
9 obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
10 obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
11 obj-$(CONFIG_PHY_MTK_XFI_TPHY) += phy-mtk-xfi-tphy.o
13 phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
14 phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DSI Controller
10 - Chun-Kuang Hu <[email protected]>
11 - Philipp Zabel <[email protected]>
12 - Jitao Shi <[email protected]>
15 The MediaTek DSI function block is a sink of the display subsystem and can
16 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
[all …]
/linux-6.14.4/drivers/gpu/drm/bridge/imx/
Dimx93-mipi-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/media-bus-format.h>
16 #include <linux/phy/phy.h>
17 #include <linux/phy/phy-mipi-dphy.h>
42 #define M(x) FIELD_PREP(M_MASK, ((x) - 2))
44 #define N(x) FIELD_PREP(N_MASK, ((x) - 1))
121 /* DPHY Databook Table 3-13 Charge-pump Programmability */
136 /* DPHY Databook Table 5-7 Frequency Ranges and Defaults */
203 static void dphy_pll_write(struct imx93_dsi *dsi, unsigned int reg, u32 value) in dphy_pll_write() argument
207 ret = regmap_write(dsi->regmap, reg, value); in dphy_pll_write()
[all …]
/linux-6.14.4/drivers/gpu/drm/msm/dsi/
Ddsi_manager.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "dsi.h"
24 struct msm_dsi *dsi[DSI_MAX]; member
39 return msm_dsim_glb.dsi[id]; in dsi_mgr_get_dsi()
44 return msm_dsim_glb.dsi[(id + 1) % DSI_MAX]; in dsi_mgr_get_other_dsi()
51 /* We assume 2 dsi nodes have the same information of bonded dsi and in dsi_mgr_parse_of()
52 * sync-mode, and only one node specifies master in case of bonded mode. in dsi_mgr_parse_of()
54 if (!msm_dsim->is_bonded_dsi) in dsi_mgr_parse_of()
55 msm_dsim->is_bonded_dsi = of_property_read_bool(np, "qcom,dual-dsi-mode"); in dsi_mgr_parse_of()
57 if (msm_dsim->is_bonded_dsi) { in dsi_mgr_parse_of()
[all …]
Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "dsi.h"
10 unsigned long host_flags = msm_dsi_host_get_mode_flags(msm_dsi->host); in msm_dsi_is_cmd_mode()
17 return msm_dsi_host_get_dsc_config(msm_dsi->host); in msm_dsi_get_dsc_config()
22 return msm_dsi_host_is_wide_bus_enabled(msm_dsi->host); in msm_dsi_wide_bus_enabled()
27 struct platform_device *pdev = msm_dsi->pdev; in dsi_get_phy()
31 phy_node = of_parse_phandle(pdev->dev.of_node, "phys", 0); in dsi_get_phy()
33 DRM_DEV_ERROR(&pdev->dev, "cannot find phy device\n"); in dsi_get_phy()
34 return -ENXIO; in dsi_get_phy()
39 msm_dsi->phy = platform_get_drvdata(phy_pdev); in dsi_get_phy()
[all …]
/linux-6.14.4/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
8 #include <dt-bindings/phy/phy.h>
13 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
20 v = (tmax - tmin) * percent; in linear_inter()
23 return max_t(s32, min_result, v - 1); in linear_inter()
35 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
36 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()
46 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7; in dsi_dphy_timing_calc_clk_zero()
47 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()
[all …]
Ddsi_phy_10nm.c2 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
11 #include "dsi.xml.h"
15 * DSI PLL 10nm - clock diagram (eg: DSI0):
20 * +---------+ | +----------+ | +----+
21 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
22 * +---------+ | +----------+ | +----+
26 * | | +----+ | |\ dsi0_pclk_mux
27 * | |--| /2 |--o--| \ |
28 * | | +----+ | \ | +---------+
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/phy/
Drockchip,px30-dsi-dphy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <[email protected]>
13 "#phy-cells":
18 - rockchip,px30-dsi-dphy
19 - rockchip,rk3128-dsi-dphy
20 - rockchip,rk3368-dsi-dphy
21 - rockchip,rk3568-dsi-dphy
[all …]
Dmixel,mipi-dsi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mixel DSI PHY for i.MX8
10 - Guido Günther <[email protected]>
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
15 electrical signals for DSI.
17 The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/display/rockchip/
Drockchip,dw-mipi-dsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Synopsys Designware MIPI DSI
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <[email protected]>
16 - enum:
17 - rockchip,px30-mipi-dsi
18 - rockchip,rk3128-mipi-dsi
[all …]

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