1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Multimedia Clock & Reset Controller
8
9maintainers:
10  - Jeffrey Hugo <[email protected]>
11  - Taniya Das <[email protected]>
12
13description: |
14  Qualcomm multimedia clock control module provides the clocks, resets and
15  power domains.
16
17properties:
18  compatible:
19    enum:
20      - qcom,mmcc-apq8064
21      - qcom,mmcc-apq8084
22      - qcom,mmcc-msm8226
23      - qcom,mmcc-msm8660
24      - qcom,mmcc-msm8960
25      - qcom,mmcc-msm8974
26      - qcom,mmcc-msm8992
27      - qcom,mmcc-msm8994
28      - qcom,mmcc-msm8996
29      - qcom,mmcc-msm8998
30      - qcom,mmcc-sdm630
31      - qcom,mmcc-sdm660
32
33  clocks:
34    minItems: 7
35    maxItems: 13
36
37  clock-names:
38    minItems: 7
39    maxItems: 13
40
41  '#clock-cells':
42    const: 1
43
44  '#reset-cells':
45    const: 1
46
47  '#power-domain-cells':
48    const: 1
49
50  reg:
51    maxItems: 1
52
53  protected-clocks:
54    description:
55      Protected clock specifier list as per common clock binding
56
57  vdd-gfx-supply:
58    description:
59      Regulator supply for the GPU_GX GDSC
60
61required:
62  - compatible
63  - reg
64  - '#clock-cells'
65  - '#reset-cells'
66  - '#power-domain-cells'
67
68additionalProperties: false
69
70allOf:
71  - if:
72      properties:
73        compatible:
74          contains:
75            enum:
76              - qcom,mmcc-apq8064
77              - qcom,mmcc-msm8960
78    then:
79      properties:
80        clocks:
81          minItems: 8
82          items:
83            - description: Board PXO source
84            - description: PLL 3 clock
85            - description: PLL 3 Vote clock
86            - description: DSI phy instance 1 dsi clock
87            - description: DSI phy instance 1 byte clock
88            - description: DSI phy instance 2 dsi clock
89            - description: DSI phy instance 2 byte clock
90            - description: HDMI phy PLL clock
91            - description: LVDS PLL clock
92
93        clock-names:
94          minItems: 8
95          items:
96            - const: pxo
97            - const: pll3
98            - const: pll8_vote
99            - const: dsi1pll
100            - const: dsi1pllbyte
101            - const: dsi2pll
102            - const: dsi2pllbyte
103            - const: hdmipll
104            - const: lvdspll
105
106  - if:
107      properties:
108        compatible:
109          contains:
110            enum:
111              - qcom,mmcc-msm8226
112    then:
113      properties:
114        clocks:
115          items:
116            - description: Board XO source
117            - description: MMSS GPLL0 voted clock
118            - description: GPLL0 voted clock
119            - description: GPLL1 voted clock
120            - description: GFX3D clock source
121            - description: DSI phy instance 0 dsi clock
122            - description: DSI phy instance 0 byte clock
123
124        clock-names:
125          items:
126            - const: xo
127            - const: mmss_gpll0_vote
128            - const: gpll0_vote
129            - const: gpll1_vote
130            - const: gfx3d_clk_src
131            - const: dsi0pll
132            - const: dsi0pllbyte
133
134  - if:
135      properties:
136        compatible:
137          contains:
138            enum:
139              - qcom,mmcc-msm8974
140    then:
141      properties:
142        clocks:
143          items:
144            - description: Board XO source
145            - description: MMSS GPLL0 voted clock
146            - description: GPLL0 voted clock
147            - description: GPLL1 voted clock
148            - description: GFX3D clock source
149            - description: DSI phy instance 0 dsi clock
150            - description: DSI phy instance 0 byte clock
151            - description: DSI phy instance 1 dsi clock
152            - description: DSI phy instance 1 byte clock
153            - description: HDMI phy PLL clock
154            - description: eDP phy PLL link clock
155            - description: eDP phy PLL vco clock
156
157        clock-names:
158          items:
159            - const: xo
160            - const: mmss_gpll0_vote
161            - const: gpll0_vote
162            - const: gpll1_vote
163            - const: gfx3d_clk_src
164            - const: dsi0pll
165            - const: dsi0pllbyte
166            - const: dsi1pll
167            - const: dsi1pllbyte
168            - const: hdmipll
169            - const: edp_link_clk
170            - const: edp_vco_div
171
172  - if:
173      properties:
174        compatible:
175          contains:
176            enum:
177              - qcom,mmcc-apq8084
178    then:
179      properties:
180        clocks:
181          items:
182            - description: Board XO source
183            - description: Board sleep source
184            - description: MMSS GPLL0 voted clock
185            - description: GPLL0 clock
186            - description: GPLL0 voted clock
187            - description: GPLL1 clock
188            - description: DSI phy instance 0 dsi clock
189            - description: DSI phy instance 0 byte clock
190            - description: DSI phy instance 1 dsi clock
191            - description: DSI phy instance 1 byte clock
192            - description: HDMI phy PLL clock
193            - description: eDP phy PLL link clock
194            - description: eDP phy PLL vco clock
195
196        clock-names:
197          items:
198            - const: xo
199            - const: sleep_clk
200            - const: mmss_gpll0_vote
201            - const: gpll0
202            - const: gpll0_vote
203            - const: gpll1
204            - const: dsi0pll
205            - const: dsi0pllbyte
206            - const: dsi1pll
207            - const: dsi1pllbyte
208            - const: hdmipll
209            - const: edp_link_clk
210            - const: edp_vco_div
211
212  - if:
213      properties:
214        compatible:
215          contains:
216            enum:
217              - qcom,mmcc-msm8994
218              - qcom,mmcc-msm8998
219              - qcom,mmcc-sdm630
220              - qcom,mmcc-sdm660
221    then:
222      required:
223        - clocks
224        - clock-names
225
226  - if:
227      properties:
228        compatible:
229          contains:
230            const: qcom,mmcc-msm8994
231    then:
232      properties:
233        clocks:
234          items:
235            - description: Board XO source
236            - description: Global PLL 0 clock
237            - description: MMSS NoC AHB clock
238            - description: GFX3D clock
239            - description: DSI phy instance 0 dsi clock
240            - description: DSI phy instance 0 byte clock
241            - description: DSI phy instance 1 dsi clock
242            - description: DSI phy instance 1 byte clock
243            - description: HDMI phy PLL clock
244
245        clock-names:
246          items:
247            - const: xo
248            - const: gpll0
249            - const: mmssnoc_ahb
250            - const: oxili_gfx3d_clk_src
251            - const: dsi0pll
252            - const: dsi0pllbyte
253            - const: dsi1pll
254            - const: dsi1pllbyte
255            - const: hdmipll
256
257  - if:
258      properties:
259        compatible:
260          contains:
261            const: qcom,mmcc-msm8996
262    then:
263      properties:
264        clocks:
265          items:
266            - description: Board XO source
267            - description: Global PLL 0 clock
268            - description: MMSS NoC AHB clock
269            - description: DSI phy instance 0 dsi clock
270            - description: DSI phy instance 0 byte clock
271            - description: DSI phy instance 1 dsi clock
272            - description: DSI phy instance 1 byte clock
273            - description: HDMI phy PLL clock
274
275        clock-names:
276          items:
277            - const: xo
278            - const: gpll0
279            - const: gcc_mmss_noc_cfg_ahb_clk
280            - const: dsi0pll
281            - const: dsi0pllbyte
282            - const: dsi1pll
283            - const: dsi1pllbyte
284            - const: hdmipll
285
286  - if:
287      properties:
288        compatible:
289          contains:
290            const: qcom,mmcc-msm8998
291    then:
292      properties:
293        clocks:
294          items:
295            - description: Board XO source
296            - description: Global PLL 0 clock
297            - description: DSI phy instance 0 dsi clock
298            - description: DSI phy instance 0 byte clock
299            - description: DSI phy instance 1 dsi clock
300            - description: DSI phy instance 1 byte clock
301            - description: HDMI phy PLL clock
302            - description: DisplayPort phy PLL link clock
303            - description: DisplayPort phy PLL vco clock
304            - description: Global PLL 0 DIV clock
305
306        clock-names:
307          items:
308            - const: xo
309            - const: gpll0
310            - const: dsi0dsi
311            - const: dsi0byte
312            - const: dsi1dsi
313            - const: dsi1byte
314            - const: hdmipll
315            - const: dplink
316            - const: dpvco
317            - const: gpll0_div
318
319  - if:
320      properties:
321        compatible:
322          contains:
323            enum:
324              - qcom,mmcc-sdm630
325              - qcom,mmcc-sdm660
326    then:
327      properties:
328        clocks:
329          items:
330            - description: Board XO source
331            - description: Board sleep source
332            - description: Global PLL 0 clock
333            - description: Global PLL 0 DIV clock
334            - description: DSI phy instance 0 dsi clock
335            - description: DSI phy instance 0 byte clock
336            - description: DSI phy instance 1 dsi clock
337            - description: DSI phy instance 1 byte clock
338            - description: DisplayPort phy PLL link clock
339            - description: DisplayPort phy PLL vco clock
340
341        clock-names:
342          items:
343            - const: xo
344            - const: sleep_clk
345            - const: gpll0
346            - const: gpll0_div
347            - const: dsi0pll
348            - const: dsi0pllbyte
349            - const: dsi1pll
350            - const: dsi1pllbyte
351            - const: dp_link_2x_clk_divsel_five
352            - const: dp_vco_divided_clk_src_mux
353
354examples:
355  # Example for MMCC for MSM8960:
356  - |
357    clock-controller@4000000 {
358      compatible = "qcom,mmcc-msm8960";
359      reg = <0x4000000 0x1000>;
360      #clock-cells = <1>;
361      #reset-cells = <1>;
362      #power-domain-cells = <1>;
363    };
364...
365