1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI 14nm PHY
8
9maintainers:
10  - Krishna Manikandan <[email protected]>
11
12allOf:
13  - $ref: dsi-phy-common.yaml#
14
15properties:
16  compatible:
17    enum:
18      - qcom,dsi-phy-14nm
19      - qcom,dsi-phy-14nm-2290
20      - qcom,dsi-phy-14nm-660
21      - qcom,dsi-phy-14nm-8953
22      - qcom,sm6125-dsi-phy-14nm
23      - qcom,sm6150-dsi-phy-14nm
24
25  reg:
26    items:
27      - description: dsi phy register set
28      - description: dsi phy lane register set
29      - description: dsi pll register set
30
31  reg-names:
32    items:
33      - const: dsi_phy
34      - const: dsi_phy_lane
35      - const: dsi_pll
36
37  vcca-supply:
38    description: Phandle to vcca regulator device node.
39
40  power-domains:
41    description:
42      A phandle and PM domain specifier for an optional power domain.
43    maxItems: 1
44
45  required-opps:
46    description:
47      A phandle to an OPP node describing the power domain's performance point.
48    maxItems: 1
49
50required:
51  - compatible
52  - reg
53  - reg-names
54
55unevaluatedProperties: false
56
57examples:
58  - |
59    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
60    #include <dt-bindings/clock/qcom,rpmh.h>
61
62    dsi-phy@ae94400 {
63        compatible = "qcom,dsi-phy-14nm";
64        reg = <0x0ae94400 0x200>,
65              <0x0ae94600 0x280>,
66              <0x0ae94a00 0x1e0>;
67        reg-names = "dsi_phy",
68                    "dsi_phy_lane",
69                    "dsi_pll";
70
71        #clock-cells = <1>;
72        #phy-cells = <0>;
73
74        vcca-supply = <&vcca_reg>;
75        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
76                 <&rpmhcc RPMH_CXO_CLK>;
77        clock-names = "iface", "ref";
78    };
79...
80