| /linux-6.14.4/drivers/ata/ |
| D | ahci_dwc.c | 122 u32 dmacr[AHCI_MAX_PORTS]; member
265 u32 port, dmacr, ts; in ahci_dwc_init_dmacr() local
284 dmacr = readl(port_mmio + AHCI_DWC_PORT_DMACR); in ahci_dwc_init_dmacr()
288 dmacr &= ~AHCI_DWC_PORT_TXTS_MASK; in ahci_dwc_init_dmacr()
289 dmacr |= FIELD_PREP(AHCI_DWC_PORT_TXTS_MASK, ts); in ahci_dwc_init_dmacr()
294 dmacr &= ~AHCI_DWC_PORT_RXTS_MASK; in ahci_dwc_init_dmacr()
295 dmacr |= FIELD_PREP(AHCI_DWC_PORT_RXTS_MASK, ts); in ahci_dwc_init_dmacr()
298 writel(dmacr, port_mmio + AHCI_DWC_PORT_DMACR); in ahci_dwc_init_dmacr()
299 dpriv->dmacr[port] = dmacr; in ahci_dwc_init_dmacr()
361 writel(dpriv->dmacr[i], port_mmio + AHCI_DWC_PORT_DMACR); in ahci_dwc_reinit_host()
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| D | sata_dwc_460ex.c | 58 u32 dmacr; /* DMA Control */ member
689 u32 dmacr = sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr); in sata_dwc_clear_dmacr() local
692 dmacr = SATA_DWC_DMACR_RX_CLEAR(dmacr); in sata_dwc_clear_dmacr()
693 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr); in sata_dwc_clear_dmacr()
695 dmacr = SATA_DWC_DMACR_TX_CLEAR(dmacr); in sata_dwc_clear_dmacr()
696 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr); in sata_dwc_clear_dmacr()
700 * sync. If it does happen, clear dmacr anyway. in sata_dwc_clear_dmacr()
703 "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n", in sata_dwc_clear_dmacr()
704 __func__, tag, hsdevp->dma_pending[tag], dmacr); in sata_dwc_clear_dmacr()
705 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, in sata_dwc_clear_dmacr()
[all …]
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| /linux-6.14.4/drivers/tty/serial/ |
| D | amba-pl011.c | 277 unsigned int dmacr; /* dma control reg */ member
550 u16 dmacr; in pl011_dma_tx_callback() local
557 dmacr = uap->dmacr; in pl011_dma_tx_callback()
558 uap->dmacr = dmacr & ~UART011_TXDMAE; in pl011_dma_tx_callback()
559 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_callback()
568 * get further refills (hence we check dmacr). in pl011_dma_tx_callback()
570 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || in pl011_dma_tx_callback()
659 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_refill()
660 pl011_write(uap->dmacr, uap, REG_DMACR); in pl011_dma_tx_refill()
694 uap->dmacr |= UART011_TXDMAE; in pl011_dma_tx_irq()
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/display/imx/ |
| D | fsl,imx-lcdc.yaml | 53 fsl,dmacr:
79 fsl,dmacr: false
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| /linux-6.14.4/sound/soc/fsl/ |
| D | p1022_rdk.c | 41 * Set the DMACR register in the GUTS
43 * The DMACR register determines the source of initiated transfers for each
88 * Here we program the DMACR and PMUXCR registers.
166 * de-program the DMACR and PMUXCR register.
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| D | p1022_ds.c | 34 * Set the DMACR register in the GUTS
36 * The DMACR register determines the source of initiated transfers for each
81 * Here we program the DMACR and PMUXCR registers.
155 * de-program the DMACR and PMUXCR register.
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| /linux-6.14.4/include/linux/fsl/ |
| D | guts.h | 106 u32 dmacr; /* 0x.0908 - DMA Control Register */ member
143 * Set the DMACR register in the GUTS
145 * The DMACR register determines the source of initiated transfers for each
160 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); in guts_set_dmacr()
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| /linux-6.14.4/drivers/video/fbdev/ |
| D | imxfb.c | 185 u_int dmacr; member
681 /* dmacr = 0 is no valid value, as we need DMA control marks. */ in imxfb_activate_var()
682 if (fbi->dmacr) in imxfb_activate_var()
683 writel(fbi->dmacr, fbi->regs + LCDC_DMACR); in imxfb_activate_var()
738 of_property_read_u32(np, "fsl,dmacr", &fbi->dmacr); in imxfb_init_fbinfo()
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| /linux-6.14.4/sound/soc/rockchip/ |
| D | rockchip_spdif.h | 33 * DMACR
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| D | rockchip_i2s.h | 128 * DMACR
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| D | rockchip_i2s_tdm.h | 137 * DMACR
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| /linux-6.14.4/drivers/spi/ |
| D | spi-rockchip.c | 146 /* Bit fields in DMACR */
540 u32 dmacr = 0; in rockchip_spi_config() local
585 dmacr |= TF_DMA_EN; in rockchip_spi_config()
587 dmacr |= RF_DMA_EN; in rockchip_spi_config()
605 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); in rockchip_spi_config()
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| D | spi-pl022.c | 396 * @dmacr: Value of DMA control Register of SSP
410 u16 dmacr; member
479 writew(chip->dmacr, SSP_DMACR(pl022->virtbase)); in restore_state()
1288 dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr); in print_current_status()
1717 chip->dmacr = 0; in pl022_setup()
1723 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, in pl022_setup()
1725 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED, in pl022_setup()
1730 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, in pl022_setup()
1732 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED, in pl022_setup()
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| D | spi-dw.h | 120 /* Bit fields in DMACR */
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| D | spi-dw-core.c | 56 DW_SPI_DBGFS_REG("DMACR", DW_SPI_DMACR),
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| /linux-6.14.4/drivers/crypto/stm32/ |
| D | stm32-cryp.c | 166 u32 dmacr; member
871 reg = stm32_cryp_read(cryp, cryp->caps->dmacr); in stm32_cryp_header_dma_callback()
872 stm32_cryp_write(cryp, cryp->caps->dmacr, reg & ~(DMACR_DOEN | DMACR_DIEN)); in stm32_cryp_header_dma_callback()
931 reg = stm32_cryp_read(cryp, cryp->caps->dmacr); in stm32_cryp_dma_callback()
932 stm32_cryp_write(cryp, cryp->caps->dmacr, reg & ~(DMACR_DOEN | DMACR_DIEN)); in stm32_cryp_dma_callback()
1006 reg = stm32_cryp_read(cryp, cryp->caps->dmacr); in stm32_cryp_header_dma_start()
1007 stm32_cryp_write(cryp, cryp->caps->dmacr, reg | DMACR_DIEN); in stm32_cryp_header_dma_start()
1079 reg = stm32_cryp_read(cryp, cryp->caps->dmacr); in stm32_cryp_dma_start()
1080 stm32_cryp_write(cryp, cryp->caps->dmacr, reg | DMACR_DOEN | DMACR_DIEN); in stm32_cryp_dma_start()
2505 .dmacr = UX500_CRYP_DMACR,
[all …]
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| /linux-6.14.4/drivers/dma/xilinx/ |
| D | xilinx_dma.c | 2547 u32 dmacr; in xilinx_vdma_channel_set_config() local
2552 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); in xilinx_vdma_channel_set_config()
2561 dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN; in xilinx_vdma_channel_set_config()
2563 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN; in xilinx_vdma_channel_set_config()
2564 dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK; in xilinx_vdma_channel_set_config()
2565 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT; in xilinx_vdma_channel_set_config()
2580 dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK; in xilinx_vdma_channel_set_config()
2581 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT; in xilinx_vdma_channel_set_config()
2586 dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK; in xilinx_vdma_channel_set_config()
2587 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT; in xilinx_vdma_channel_set_config()
[all …]
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| /linux-6.14.4/arch/arm/boot/dts/nxp/imx/ |
| D | imx27-apf27dev.dts | 94 fsl,dmacr = <0x00020010>;
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| D | imx27-eukrea-mbimxsd27-baseboard.dts | 91 fsl,dmacr = <0x00040060>;
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| D | imx25-pdk.dts | 243 fsl,dmacr = <0x00020010>;
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| D | imx27-phytec-phycore-rdk.dts | 71 fsl,dmacr = <0x00020010>;
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| /linux-6.14.4/drivers/dma/ |
| D | mpc512x_dma.c | 95 u32 dmacr; /* DMA control register */ member
1023 out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_ERCA); in mpc_dma_probe()
1034 out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_EDCG | in mpc_dma_probe()
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| /linux-6.14.4/drivers/net/ethernet/intel/i40e/ |
| D | i40e_adminq_cmd.h | 428 __le32 dmacr; member
|