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/linux-6.14.4/drivers/mmc/host/
Dsdhci-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
23 #include "sdhci-cqhci.h"
24 #include "sdhci-pltfm.h"
123 #define INVALID_TUNING_PHASE -1
140 /* Max load for eMMC Vdd-io supply */
146 /* Max load for SD Vdd-io supply */
150 msm_host->var_ops->msm_readl_relaxed(host, offset)
153 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
[all …]
Dsdhci-esdhc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
26 /* pltfm-specific */
89 /* DLL Config 0 Register */
95 /* DLL Config 1 Register */
99 /* DLL Status 0 Register */
Dsdhci-xenon-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
17 #include "sdhci-pltfm.h"
18 #include "sdhci-xenon.h"
128 /* Offset of DLL Control register */
132 /* DLL Update Enable bit */
209 params = devm_kzalloc(mmc_dev(host->mmc), sizeof(*params), GFP_KERNEL); in xenon_alloc_emmc_phy()
211 return -ENOMEM; in xenon_alloc_emmc_phy()
213 priv->phy_params = params; in xenon_alloc_emmc_phy()
214 if (priv->phy_type == EMMC_5_0_PHY) in xenon_alloc_emmc_phy()
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Dsdhci-st.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Based on sdhci-cns3xxx.c
18 #include "sdhci-pltfm.h"
88 #define ST_TOP_MMC_DLY_FIX_OFF(x) (x - 0x8)
90 /* TOP config registers to manage static and dynamic delay */
102 /* register to provide the phase-shift value for DLL */
119 * DLL procedure has finished before switching to ultra-speed modes.
139 * flashSS sub-system which needs to be configured to be compliant to eMMC 4.5
145 struct mmc_host *mhost = host->mmc; in st_mmcss_cconfig()
148 if (!of_device_is_compatible(np, "st,sdhci-stih407")) in st_mmcss_cconfig()
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Dsdhci-esdhc-imx.c1 // SPDX-License-Identifier: GPL-2.0
5 * derived from the OF-version.
23 #include <linux/mmc/slot-gpio.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
30 #include "sdhci-esdhc.h"
74 /* dll control register */
83 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
85 /* strobe dll register */
141 * open ended multi-blk IO. Otherwise the TC INT wouldn't
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/linux-6.14.4/arch/arm/mach-omap2/
Dsleep34xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Karthik Dasu <karthik-[email protected]>
9 * Richard Woodruff <r-[email protected]>
57 * with non-Thumb-2-capable firmware.
86 .arch armv7-a
89 stmfd sp!, {r4 - r11, lr} @ save registers on stack
103 ldmfd sp!, {r4 - r11, pc}
115 * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
121 * - only the minimum set of functions gets copied to internal SRAM at boot
122 * and after wake-up from OFF mode, cf. omap_push_sram_idle. The function
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/linux-6.14.4/Documentation/devicetree/bindings/mmc/
Dsdhci-msm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bjorn Andersson <[email protected]>
11 - Konrad Dybcio <[email protected]>
20 - enum:
21 - qcom,sdhci-msm-v4
23 - items:
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/linux-6.14.4/arch/arm/mach-orion5x/
Dtsx09-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * QNAP TS-x09 Boards common functions
15 #include "tsx09-common.h"
19 * QNAP TS-x09 specific power off method via UART1-attached PIC
29 pr_info("%s: triggering power-off...\n", __func__); in qnap_tsx09_power_off()
33 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_tsx09_power_off()
40 /* send the power-off command 'A' to PIC */ in qnap_tsx09_power_off()
55 return n - '0'; in qnap_tsx09_parse_hex_nibble()
58 return n - 'A' + 10; in qnap_tsx09_parse_hex_nibble()
61 return n - 'a' + 10; in qnap_tsx09_parse_hex_nibble()
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/linux-6.14.4/drivers/spi/
Datmel-quadspi.c1 // SPDX-License-Identifier: GPL-2.0
11 * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
17 #include <linux/dma-mapping.h>
29 #include <linux/spi/spi-mem.h>
54 #define QSPI_DLLCFG 0x0058 /* DLL Configuration Register */
91 #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
196 /* Bitfields in QSPI_DLLCFG (DLL Configuration Register) */
199 /* Bitfields in QSPI_PCALCFG (DLL Pad Calibration Configuration Register) */
208 /* Bitfields in QSPI_PCALBP (DLL Pad Calibration Bypass Register) */
236 * struct atmel_qspi_pcal - Pad Calibration Clock Division
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Dspi-nxp-fspi.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2019-2020 NXP
14 * FlexSPI controller is driven by the LUT(Look-up Table) registers
15 * LUT registers are a look-up-table for sequences of instructions.
19 * LUTs are being created at run-time based on the commands passed
20 * from the spi-mem framework, thus using single LUT index.
26 * Based on SPI MEM interface and spi-fsl-qspi.c driver.
58 #include <linux/spi/spi-mem.h>
300 #define LUT_PAD(x) (fls(x) - 1)
306 * ---------------------------------------------------
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Dspi-cadence-xspi.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (C) 2020-21 Cadence
19 #include <linux/spi/spi-mem.h>
27 #define CDNS_XSPI_NAME "cadence-xspi"
31 * configure XSPI controller pin-strap settings
43 /* PHY DLL slave control register */
46 /* DLL PHY control register */
93 /* Controller config register */
157 FIELD_PREP(CDNS_XSPI_CMD_P1_R1_ADDR0, (op)->addr.val & 0xff))
160 FIELD_PREP(CDNS_XSPI_CMD_P1_R2_ADDR1, ((op)->addr.val >> 8) & 0xFF) | \
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/linux-6.14.4/include/linux/ssb/
Dssb_driver_gige.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 #define SSB_GIGE_PCICFG 0x0800 /* PCI config space (256 bytes) */
25 #define SSB_GIGE_TMSHIGH_RGMII 0x00010000 /* Have an RGMII PHY-bus */
29 #define SSB_GIGE_TMSLOW_DLLEN 0x01000000 /* Enable DLL controls */
62 return container_of(pdev->bus->ops, struct ssb_gige, pci_ops); in pdev_to_ssb_gige()
69 return (dev ? dev->has_rgmii : 0); in ssb_gige_is_rgmii()
77 return !!(dev->dev->bus->sprom.boardflags_lo & in ssb_gige_have_roboswitch()
87 return ((dev->dev->bus->chip_id == 0x4785) && in ssb_gige_one_dma_at_once()
88 (dev->dev->bus->chip_rev < 2)); in ssb_gige_one_dma_at_once()
97 return (dev->dev->bus->chip_id == 0x4785); in ssb_gige_must_flush_posted_writes()
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/linux-6.14.4/arch/mips/cavium-octeon/executive/
Dcvmx-spi.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 #include <asm/octeon/cvmx-config.h>
36 #include <asm/octeon/cvmx-pko.h>
37 #include <asm/octeon/cvmx-spi.h>
39 #include <asm/octeon/cvmx-spxx-defs.h>
40 #include <asm/octeon/cvmx-stxx-defs.h>
41 #include <asm/octeon/cvmx-srxx-defs.h>
108 int res = -1; in cvmx_spi_start_interface()
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/linux-6.14.4/drivers/phy/microchip/
Dlan966x_serdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/phy/phy-lan966x-serdes.h>
189 lan_rmw(HSIO_SD_CFG_LANE_10BIT_SEL_SET(res_struct->lane_10bit_sel) | in lan966x_sd6g40_reg_cfg()
190 HSIO_SD_CFG_RX_RATE_SET(res_struct->rx_rate) | in lan966x_sd6g40_reg_cfg()
191 HSIO_SD_CFG_TX_RATE_SET(res_struct->tx_rate) | in lan966x_sd6g40_reg_cfg()
192 HSIO_SD_CFG_TX_INVERT_SET(res_struct->tx_invert) | in lan966x_sd6g40_reg_cfg()
193 HSIO_SD_CFG_RX_INVERT_SET(res_struct->rx_invert) | in lan966x_sd6g40_reg_cfg()
194 HSIO_SD_CFG_LANE_LOOPBK_EN_SET(res_struct->lane_loopbk_en) | in lan966x_sd6g40_reg_cfg()
205 macro->ctrl->regs, HSIO_SD_CFG(idx)); in lan966x_sd6g40_reg_cfg()
207 lan_rmw(HSIO_MPLL_CFG_MPLL_MULTIPLIER_SET(res_struct->mpll_multiplier) | in lan966x_sd6g40_reg_cfg()
[all …]
/linux-6.14.4/drivers/tty/serial/
Domap-serial.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for OMAP-UART controller.
16 * this driver as required for the omap-platform.
38 #include <linux/platform_data/serial-omap.h>
79 #define OMAP_UART_DMA_CH_FREE -1
136 unsigned char dll; member
176 offset <<= up->port.regshift; in serial_in()
177 return readw(up->port.membase + offset); in serial_in()
182 offset <<= up->port.regshift; in serial_out()
183 writew(value, up->port.membase + offset); in serial_out()
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/linux-6.14.4/drivers/tty/serial/8250/
D8250_port.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
244 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
245 * workaround of errata A-008006 which states that tx_loadsz should
257 .name = "Palmchip BK-3103",
328 unsigned char dll = serial_in(up, UART_DLL); in default_serial_dl_read() local
331 return dll | dlm << 8; in default_serial_dl_read()
344 offset = offset << p->regshift; in hub6_serial_in()
345 outb(p->hub6 - 1 + offset, p->iobase); in hub6_serial_in()
346 return inb(p->iobase + 1); in hub6_serial_in()
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/linux-6.14.4/drivers/net/ethernet/cavium/octeon/
Docteon_mgmt.c6 * Copyright (C) 2009-2012 Cavium, Inc
10 #include <linux/dma-mapping.h>
27 #include <asm/octeon/cvmx-mixx-defs.h>
28 #include <asm/octeon/cvmx-agl-defs.h>
162 spin_lock_irqsave(&p->lock, flags); in octeon_mgmt_set_rx_irq()
163 mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); in octeon_mgmt_set_rx_irq()
165 cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); in octeon_mgmt_set_rx_irq()
166 spin_unlock_irqrestore(&p->lock, flags); in octeon_mgmt_set_rx_irq()
174 spin_lock_irqsave(&p->lock, flags); in octeon_mgmt_set_tx_irq()
175 mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); in octeon_mgmt_set_tx_irq()
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/linux-6.14.4/drivers/net/dsa/microchip/
Dlan937x_main.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2024 Microchip Technology Inc.
21 /* marker for ports without built-in PHY */
25 * lan9370_phy_addr - Mapping of LAN9370 switch ports to PHY addresses.
28 * where ports 1-4 are connected to integrated 100BASE-T1 PHYs, and
41 * lan9371_phy_addr - Mapping of LAN9371 switch ports to PHY addresses.
55 * lan9372_phy_addr - Mapping of LAN9372 switch ports to PHY addresses.
71 * lan9373_phy_addr - Mapping of LAN9373 switch ports to PHY addresses.
87 * lan9374_phy_addr - Mapping of LAN9374 switch ports to PHY addresses.
115 * lan937x_create_phy_addr_map - Create port-to-PHY address map for MDIO bus.
[all …]
/linux-6.14.4/drivers/firmware/xilinx/
Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2022 Xilinx, Inc.
6 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
14 #include <linux/arm-smccc.h>
27 #include <linux/firmware/xlnx-zynqmp.h>
28 #include <linux/firmware/xlnx-event-manager.h>
29 #include "zynqmp-debug.h"
36 /* BOOT_PIN_CTRL- Used to control the mode pins after boot */
38 /* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
53 * struct zynqmp_devinfo - Structure for Zynqmp device instance
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/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dqcm2290.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
10 #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interconnect/qcom,qcm2290.h>
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Dsm6125.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
7 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/dma/qcom-gpi.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom-rpmpd.h>
15 interrupt-parent = <&intc>;
16 #address-cells = <2>;
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/linux-6.14.4/arch/arm64/boot/dts/socionext/
Duniphier-pxs3.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-pxs3";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
20 #address-cells = <2>;
[all …]
Duniphier-ld20.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/uniphier-gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-ld20";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dci_smumgr.c100 return -EINVAL; in ci_set_smc_sram_address()
103 cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr); in ci_set_smc_sram_address()
104 PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0); in ci_set_smc_sram_address()
120 return -EINVAL; in ci_copy_bytes_to_smc()
134 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); in ci_copy_bytes_to_smc()
137 byte_count -= 4; in ci_copy_bytes_to_smc()
151 original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0); in ci_copy_bytes_to_smc()
153 extra_shift = 8 * (4 - byte_count); in ci_copy_bytes_to_smc()
158 byte_count--; in ci_copy_bytes_to_smc()
170 cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data); in ci_copy_bytes_to_smc()
[all …]
Dtonga_smumgr.c102 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
110 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
114 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
117 /* De-assert reset */ in tonga_start_in_protection_mode()
118 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
122 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
126 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_protection_mode()
142 if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, in tonga_start_in_protection_mode()
145 return -EINVAL; in tonga_start_in_protection_mode()
164 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, in tonga_start_in_non_protection_mode()
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