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/linux-6.14.4/Documentation/devicetree/bindings/soc/altera/
Daltr,sys-mgr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/altera/altr,sys-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dinh Nguyen <[email protected]>
15 - description: Cyclone5/Arria5/Arria10
16 const: altr,sys-mgr
17 - description: Stratix10 SoC
19 - const: altr,sys-mgr-s10
20 - const: altr,sys-mgr
[all …]
/linux-6.14.4/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10_swvp.dts1 // SPDX-License-Identifier: GPL-2.0
10 compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
27 stdout-path = "serial1:115200n8";
28 linux,initrd-start = <0x10000000>;
29 linux,initrd-end = <0x125c8324>;
39 enable-method = "spin-table";
40 cpu-release-addr = <0x0 0x0000fff8>;
43 &cpu1 {
44 enable-method = "spin-table";
45 cpu-release-addr = <0x0 0x0000fff8>;
[all …]
/linux-6.14.4/arch/mips/bmips/
Dsetup.c24 #include <asm/cpu-type.h>
27 #include <asm/smp-ops.h>
38 * CBR addr doesn't change and we can cache it.
39 * For broken SoC/Bootloader CBR addr might also be provided via DT
40 * with "brcm,bmips-cbr-reg" in the "cpus" node.
65 * load address to a non-conflicting region (e.g. via in bcm3384_viper_quirks()
71 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our in bcm3384_viper_quirks()
85 * The bootloader has set up the CPU1 reset vector at in bcm63xx_fixup_cpu1()
88 * The bootloader has also set up CPU1 to respond to the wrong in bcm63xx_fixup_cpu1()
90 * Here we will start up CPU1 in the background and ask it to in bcm63xx_fixup_cpu1()
[all …]
/linux-6.14.4/arch/arm/mach-omap2/
Domap-smp.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/irqchip/arm-gic.h>
25 #include "omap-secure.h"
26 #include "omap-wakeupgen.h"
87 * BIT(27) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
89 * BIT(25) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
149 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. in omap4_secondary_init()
150 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA in omap4_secondary_init()
151 * init and for CPU1, a secure PPA API provided. CPU0 must be ON in omap4_secondary_init()
152 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+. in omap4_secondary_init()
[all …]
/linux-6.14.4/arch/arm/mach-socfpga/
Dsocfpga.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012-2015 Altera Corporation
26 np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr"); in socfpga_sysmgr_init()
28 if (of_property_read_u32(np, "cpu1-start-addr", in socfpga_sysmgr_init()
30 pr_err("SMP: Need cpu1-start-addr in device tree.\n"); in socfpga_sysmgr_init()
38 np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr"); in socfpga_sysmgr_init()
41 np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl"); in socfpga_sysmgr_init()
108 "altr,socfpga-arria10",
/linux-6.14.4/arch/mips/bcm63xx/
Dprom.c14 #include <asm/smp-ops.h>
25 /* Cache CBR addr before CPU/DMA setup */ in prom_init()
82 * The bootloader has set up the CPU1 reset vector at in prom_init()
85 * The bootloader has also set up CPU1 to respond to the wrong in prom_init()
87 * Here we will start up CPU1 in the background and ask it to in prom_init()
/linux-6.14.4/arch/arm/boot/dts/intel/socfpga/
Dsocfpga_arria5.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
16 clock-frequency = <25000000>;
22 broken-cd;
23 bus-width = <4>;
24 cap-mmc-highspeed;
25 cap-sd-highspeed;
26 clk-phase-sd-hs = <0>, <135>;
30 cpu1-start-addr = <0xffd080c4>;
Dsocfpga_cyclone5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
16 clock-frequency = <25000000>;
22 broken-cd;
23 bus-width = <4>;
24 cap-mmc-highspeed;
25 cap-sd-highspeed;
26 clk-phase-sd-hs = <0>, <135>;
30 cpu1-start-addr = <0xffd080c4>;
Dsocfpga_vt.dts1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
11 compatible = "altr,socfpga-vt", "altr,socfpga";
27 clock-frequency = <10000000>;
33 broken-cd;
34 bus-width = <4>;
35 cap-mmc-highspeed;
36 cap-sd-highspeed;
40 phy-mode = "gmii";
45 clock-frequency = <7000000>;
[all …]
Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
/linux-6.14.4/drivers/net/wireless/intel/iwlwifi/fw/
Dpaging.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2012-2014, 2018-2019, 2021 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
7 #include "iwl-drv.h"
15 if (!fwrt->fw_paging_db[0].fw_paging_block) in iwl_free_fw_paging()
19 struct iwl_fw_paging *paging = &fwrt->fw_paging_db[i]; in iwl_free_fw_paging()
21 if (!paging->fw_paging_block) { in iwl_free_fw_paging()
28 dma_unmap_page(fwrt->trans->dev, paging->fw_paging_phys, in iwl_free_fw_paging()
29 paging->fw_paging_size, DMA_BIDIRECTIONAL); in iwl_free_fw_paging()
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/linux-6.14.4/arch/csky/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
41 select ARCH_WANT_FRAME_POINTERS if !CPU_CK610 && $(cc-option,-mbacktrace)
150 In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not.
185 # VA_BITS - PAGE_SHIFT - 3
235 prompt "C-SKY PMU type"
265 bool "Tightly-Coupled/Sram Memory"
268 The implementation are not only used by TCM (Tightly-Coupled Memory)
271 re-used directly.
315 bool "Symmetric Multi-Processing (SMP) support for C-SKY"
320 int "Maximum number of CPUs (2-32)"
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/linux-6.14.4/mm/
Dvmalloc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * SMP-safe vmalloc/vfree/ioremap, Tigran Aivazian <[email protected]>, May 2000
51 #include "pgalloc-track.h"
54 static unsigned int __ro_after_init ioremap_max_page_shift = BITS_PER_LONG - 1;
81 unsigned long addr = (unsigned long)kasan_reset_tag(x); in is_vmalloc_addr() local
83 return addr >= VMALLOC_START && addr < VMALLOC_END; in is_vmalloc_addr()
94 static int vmap_pte_range(pmd_t *pmd, unsigned long addr, unsigned long end, in vmap_pte_range() argument
104 pte = pte_alloc_kernel_track(pmd, addr, mask); in vmap_pte_range()
106 return -ENOMEM; in vmap_pte_range()
117 size = arch_vmap_pte_range_map_size(addr, end, pfn, max_page_shift); in vmap_pte_range()
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Dhuge_memory.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/backing-dev.h>
39 #include <linux/memory-tiers.h>
93 if (!vma->vm_file) in file_thp_enabled()
96 inode = file_inode(vma->vm_file); in file_thp_enabled()
98 return !inode_is_open_for_write(inode) && S_ISREG(inode->i_mode); in file_thp_enabled()
123 if (!vma->vm_mm) /* vdso */ in __thp_vma_allowable_orders()
150 unsigned long addr; in __thp_vma_allowable_orders() local
153 addr = vma->vm_end - (PAGE_SIZE << order); in __thp_vma_allowable_orders()
154 if (thp_vma_suitable_order(vma, addr, order)) in __thp_vma_allowable_orders()
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Dswapfile.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <linux/blk-cgroup.h>
31 #include <linux/backing-dev.h>
77 static int least_priority = -1;
101 * swap_info_struct changes between not-full/full, it needs to
102 * add/remove itself to/from this list, but the swap_info_struct->lock
104 * before any swap_info_struct->lock.
139 * off-list bit in the atomic counter, updates no longer need any lock
145 #define SWAP_USAGE_OFFLIST_BIT (1UL << (BITS_PER_TYPE(atomic_t) - 2))
149 return atomic_long_read(&si->inuse_pages) & SWAP_USAGE_COUNTER_MASK; in swap_usage_in_pages()
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/linux-6.14.4/drivers/sbus/char/
Denvctrl.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * VT - The implementation is to support Sun Microelectronics (SME) platform
8 * controller to access pcf8591 (8-bit A/D and D/A converter) and
9 * pcf8571 (256 x 8-bit static low-voltage RAM with I2C-bus interface).
11 * http://www-eu2.semiconductors.com/pip/PCF8584P
12 * http://www-eu2.semiconductors.com/pip/PCF8574AP
13 * http://www-eu2.semiconductors.com/pip/PCF8591P
15 * EB - Added support for CP1500 Global Address and PS/Voltage monitoring.
18 * DB - Audit every copy_to_user in envctrl_read.
74 #define OBD_SEND_START 0xc5 /* value to generate I2c_bus START condition */
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/linux-6.14.4/arch/mips/include/asm/sgi/
Dheart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2004-2007 Stanislaw Skowronek <[email protected]>
7 * 2007-2015 Joshua Kinard <[email protected]>
27 * struct ip30_heart_regs - struct that maps IP30 HEART registers.
28 * @mode: HEART_MODE - Purpose Unknown, machine reset called from here.
29 * @sdram_mode: HEART_SDRAM_MODE - purpose unknown.
30 * @mem_refresh: HEART_MEM_REF - purpose unknown.
31 * @mem_req_arb: HEART_MEM_REQ_ARB - purpose unknown.
32 * @mem_cfg.q: union for 64bit access to HEART_MEMCFG - 4x 64bit registers.
33 * @mem_cfg.l: union for 32bit access to HEART_MEMCFG - 8x 32bit registers.
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/linux-6.14.4/arch/arm/boot/dts/nvidia/
Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
8 #include "tegra20-cpu-opp.dtsi"
9 #include "tegra20-cpu-opp-microvolt.dtsi"
25 stdout-path = "serial0:115200n8";
44 vdd-supply = <&hdmi_vdd_reg>;
45 pll-supply = <&hdmi_pll_reg>;
47 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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Dtegra30-asus-transformer-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/gpio-keys.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
8 #include "tegra30-cpu-opp.dtsi"
9 #include "tegra30-cpu-opp-microvolt.dtsi"
12 chassis-type = "convertible";
31 * pre-existing /chosen node to be available to insert the
37 trusted-foundations {
38 compatible = "tlm,trusted-foundations";
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Dtegra30-lg-x3.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/gpio-keys.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
6 #include <dt-bindings/mfd/max77620.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-cpu-opp.dtsi"
11 #include "tegra30-cpu-opp-microvolt.dtsi"
14 chassis-type = "handset";
30 * pre-existing /chosen node to be available to insert the
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/linux-6.14.4/arch/arm/boot/dts/broadcom/
Dbcm2711.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
[all …]
/linux-6.14.4/drivers/net/wireless/intel/iwlwifi/pcie/
Dtrans.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2007-2015, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
18 #include "iwl-drv.h"
19 #include "iwl-trans.h"
20 #include "iwl-csr.h"
21 #include "iwl-prph.h"
22 #include "iwl-scd.h"
23 #include "iwl-agn-hw.h"
[all …]
/linux-6.14.4/arch/arm/boot/dts/samsung/
Dexynos4212-tab3.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include "exynos4412-ppmu-common.dtsi"
12 #include "exynos-mfc-reserved-memory.dtsi"
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/leds/common.h>
16 #include <dt-bindings/input/gpio-keys.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
[all …]
/linux-6.14.4/kernel/time/
Dtimer.c1 // SPDX-License-Identifier: GPL-2.0
7 * 1997-01-28 Modified by Finn Arne Gangstad to make timers scale better.
9 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
11 * 1998-12-24 Fixed a xtime SMP race (we need the xtime_lock rw spinlock to
14 * 1999-03-10 Improved NTP compatibility by Ulrich Windl
15 * 2002-05-31 Move sys_sysinfo here and make its locking sane, Robert Love
16 * 2000-10-05 Implemented scalable SMP per-CPU timer handling.
33 #include <linux/posix-timers.h>
54 #include "tick-internal.h"
106 * 0 0 1 ms 0 ms - 63 ms
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/linux-6.14.4/Documentation/
Dmemory-barriers.txt19 documentation at tools/memory-model/. Nevertheless, even this memory
37 Note also that it is possible that a barrier may be a no-op for an
48 - Device operations.
49 - Guarantees.
53 - Varieties of memory barrier.
54 - What may not be assumed about memory barriers?
55 - Address-dependency barriers (historical).
56 - Control dependencies.
57 - SMP barrier pairing.
58 - Examples of memory barrier sequences.
[all …]

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